projects
/
calu.git
/ commitdiff
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
| commitdiff |
tree
raw
|
patch
|
inline
| side by side (parent:
f93d3c8
)
removed 7seg from DT
author
Martin Perner
<martin@perner.cc>
Wed, 19 Jan 2011 18:24:33 +0000
(19:24 +0100)
committer
Martin Perner
<martin@perner.cc>
Thu, 20 Jan 2011 10:15:19 +0000
(11:15 +0100)
cpu/src/core_pkg.vhd
patch
|
blob
|
history
cpu/src/core_top.vhd
patch
|
blob
|
history
cpu/src/writeback_stage.vhd
patch
|
blob
|
history
cpu/src/writeback_stage_b.vhd
patch
|
blob
|
history
dt/.gitignore
patch
|
blob
|
history
dt/dt.qpf
patch
|
blob
|
history
diff --git
a/cpu/src/core_pkg.vhd
b/cpu/src/core_pkg.vhd
index 8f24a135ef667ddd6388388fc5608c4f3d16ca7a..bd13a9c1ac4445c9a12a1c574215f47478afdbf5 100644
(file)
--- a/
cpu/src/core_pkg.vhd
+++ b/
cpu/src/core_pkg.vhd
@@
-159,10
+159,10
@@
package core_pkg is
im_addr : out gp_register_t;
im_data : out gp_register_t;
im_addr : out gp_register_t;
im_data : out gp_register_t;
- sseg0 : out std_logic_vector(0 to 6);
- sseg1 : out std_logic_vector(0 to 6);
- sseg2 : out std_logic_vector(0 to 6);
- sseg3 : out std_logic_vector(0 to 6);
+
--
sseg0 : out std_logic_vector(0 to 6);
+
--
sseg1 : out std_logic_vector(0 to 6);
+
--
sseg2 : out std_logic_vector(0 to 6);
+
--
sseg3 : out std_logic_vector(0 to 6);
int_req : out interrupt_t
int_req : out interrupt_t
diff --git
a/cpu/src/core_top.vhd
b/cpu/src/core_top.vhd
index f5354e33f4d5f9f0cf4a0dc130a07793830c24e6..a8d3bde57bfbc280729be3cd777bf3733779c9bf 100644
(file)
--- a/
cpu/src/core_top.vhd
+++ b/
cpu/src/core_top.vhd
@@
-18,12
+18,12
@@
entity core_top is
-- uart
bus_tx : out std_logic;
bus_rx : in std_logic;
-- uart
bus_tx : out std_logic;
bus_rx : in std_logic;
- led2 : out std_logic
;
+ led2 : out std_logic
- sseg0 : out std_logic_vector(0 to 6);
- sseg1 : out std_logic_vector(0 to 6);
- sseg2 : out std_logic_vector(0 to 6);
- sseg3 : out std_logic_vector(0 to 6)
+
--
sseg0 : out std_logic_vector(0 to 6);
+
--
sseg1 : out std_logic_vector(0 to 6);
+
--
sseg2 : out std_logic_vector(0 to 6);
+
--
sseg3 : out std_logic_vector(0 to 6)
);
end core_top;
);
end core_top;
@@
-180,7
+180,8
@@
begin
reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
-- instruction memory program port :D
new_im_data, im_addr, im_data,
reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
-- instruction memory program port :D
new_im_data, im_addr, im_data,
- sseg0, sseg1, sseg2, sseg3, int_req);
+ --sseg0, sseg1, sseg2, sseg3,
+ int_req);
syn: process(sys_clk, sys_res, soft_res)
syn: process(sys_clk, sys_res, soft_res)
diff --git
a/cpu/src/writeback_stage.vhd
b/cpu/src/writeback_stage.vhd
index ea82a1edc3e045cd22365abe7181a757bdab8069..ff31450b4cf8b72ee491fa393e2509c44b4c9bc5 100644
(file)
--- a/
cpu/src/writeback_stage.vhd
+++ b/
cpu/src/writeback_stage.vhd
@@
-44,10
+44,10
@@
entity writeback_stage is
im_addr : out gp_register_t;
im_data : out gp_register_t;
im_addr : out gp_register_t;
im_data : out gp_register_t;
- sseg0 : out std_logic_vector(0 to 6);
- sseg1 : out std_logic_vector(0 to 6);
- sseg2 : out std_logic_vector(0 to 6);
- sseg3 : out std_logic_vector(0 to 6);
+
--
sseg0 : out std_logic_vector(0 to 6);
+
--
sseg1 : out std_logic_vector(0 to 6);
+
--
sseg2 : out std_logic_vector(0 to 6);
+
--
sseg3 : out std_logic_vector(0 to 6);
int_req : out interrupt_t
int_req : out interrupt_t
diff --git
a/cpu/src/writeback_stage_b.vhd
b/cpu/src/writeback_stage_b.vhd
index 6a3a4e6c0e11ef5b500e29f9ba24e5ed698d9c40..569f2c68ed2e280c0367745ce07ab06ee2aa8d38 100755
(executable)
--- a/
cpu/src/writeback_stage_b.vhd
+++ b/
cpu/src/writeback_stage_b.vhd
@@
-95,6
+95,8
@@
imp : extension_imp
new_im_data_out
);
new_im_data_out
);
+ rem7seg: if "a" /= "a" generate
+
altera_7seg: if FPGATYPE /= "s3e" generate
sseg : extension_7seg
generic map(
altera_7seg: if FPGATYPE /= "s3e" generate
sseg : extension_7seg
generic map(
@@
-103,13
+105,15
@@
sseg : extension_7seg
port map(
clk,
reset,
port map(
clk,
reset,
- ext_7seg,
- sseg0,
- sseg1,
- sseg2,
- sseg3
+ --ext_7seg,
+ ext_7seg
+ --sseg0,
+ --sseg1,
+ --sseg2,
+ --sseg3
);
end generate;
);
end generate;
+ end generate;
interrupt : extension_interrupt
generic map(
interrupt : extension_interrupt
generic map(
diff --git
a/dt/.gitignore
b/dt/.gitignore
index c949f285101195928255d3ea0aecda8be19337e6..2429abe766fd3097790322704852b559a4c3ee08 100644
(file)
--- a/
dt/.gitignore
+++ b/
dt/.gitignore
@@
-1,18
+1,12
@@
db/
incremental_db
work/
db/
incremental_db
work/
-dt.asm.rpt
-dt.done
-dt.dpf
-dt.fit.rpt
-dt.fit.summary
-dt.flow.rpt
-dt.map.rpt
-dt.map.summary
-dt.pin
-dt.pof
-dt.rbf
-dt.sof
+*.done
+*.dpf
+*.pin
+*.pof
+*.rbf
+*.sof
dt.*.rpt
dt.*.summary
output_file.pof
dt.*.rpt
dt.*.summary
output_file.pof
diff --git
a/dt/dt.qpf
b/dt/dt.qpf
index 86412f03cff6a563d59a8731d439b313816713a2..e7fbff1b1c353edb88e4e6eb984cacccf6736982 100644
(file)
--- a/
dt/dt.qpf
+++ b/
dt/dt.qpf
@@
-18,13
+18,14
@@
#
# Quartus II
# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
#
# Quartus II
# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-# Date created = 1
5:08:54 December 16, 2010
+# Date created = 1
2:37:50 January 18, 2011
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "10.0"
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "10.0"
-DATE = "1
5:08:54 December 16, 2010
"
+DATE = "1
2:37:50 January 18, 2011
"
# Revisions
# Revisions
+PROJECT_REVISION = "DSE"
PROJECT_REVISION = "dt"
PROJECT_REVISION = "dt"