--- /dev/null
+.data
+.org 0x10
+inputdata:
+;8 * 8 4
+.fill 1, 0x382A3834
+;1 X * 8
+.fill 1, 0x31582A38
+;+ D X -
+.fill 1, 0x2B44582D
+;P \xF8 J D
+.fill 1, 0x50F84A44
+;+ * 8 6
+.fill 1, 0x2B2A3836
+;\000 \020 I D
+.fill 1, 0x00204944
+;~ < \000 \000
+.fill 1, 0x7E3C0000
+;8 P \005 J
+.fill 1, 0x3850054A
+;* 8
+.fill 1, 0x2A38
+
+stack:
+.fill 256, 0
+
+;needed for jumps
+;assuming that no more than 42 instr are used
+instrtable:
+.fill 42, 0
+
+prog_eof:
+.ifill ldw r0, 0-4(r3);0xE701FFFC
+.ifill ret+
+
+prog_mul:
+.ifill subi r3, r3, 4;0xE1998020
+.ifill ldw r6, 0(r3);0xe7318000
+.ifill ldw r7, 0-4(r3);0xe739fffc
+.ifill ldis r8, 0;0xed400004
+.ifill mov r0, r7;0xe1038000
+.ifill andx r0, 1;0xe2800008
+.ifill adddnz r8, r8, r6;0x00443001
+.ifill subinz r7, r7, 1;0x01bb8008
+.ifill addizs r7, r7, 0;0x113b8000
+;loop:
+.ifill adddnz r8, r8, r6;0x00443001
+.ifill adddnz r8, r8, r6;0x00443001
+.ifill subi r7, r7, 2;0xe1bb8010
+.fill 0x0b7ffe83;brnz+ loop
+.ifill stw r8, 0-4(r3);0xe7c1fffc
+
+prog_consts:
+.fill 0xed300004;ldis r6, CONST
+.ifill stw r6, 0(r3);0xe7b18000
+.ifill addi r3, r3, 4;0xe1198020
+
+prog_add:
+.ifill subi r3, r3, 4;0xe1998020
+.ifill ldw r6, 0(r3);0xe7318000
+.ifill ldw r7, 0-4(r3);0xe739fffc
+.ifill add r7, r7, r6;0xe03bb000
+.ifill stw r7, 0-4(r3);0xe7b9fffc
+
+prog_sub:
+.ifill subi r3, r3, 4;0xe1998020
+.ifill ldw r6, 0(r3);0xe7318000
+.ifill ldw r7, 0-4(r3);0xe739fffc
+.ifill sub r7, r7, r6;0xe0bbb000
+.ifill stw r7, 0-4(r3);0xe7b9fffc
+
+prog_lessthan:
+.ifill subi r3, r3, 4;0xe1998020
+.ifill ldw r6, 0(r3);0xe7318000
+.ifill ldw r7, 0-4(r3);0xe739fffc
+.ifill cmp r7, r6;0xec3b0000
+.ifill stwlt r14, 0-4(r3);
+.ifill stwge r15, 0-4(r3);
+
+prog_dup:
+.ifill ldw r6, 0-4(r3);0xe731fffc
+.ifill stw r6, 0(r3);0xe7b18000
+.ifill addi r3, r3, 4;0xe1198020
+
+prog_jmp:
+.ifill subi r3, r3, 4;0xe1998020
+.ifill ldw r6, 0(r3);0xe7318000
+.ifill cmpi r6,0;0xecb00000
+;static calced
+.fill 1, 0x1b000103;breq- vm_next
+.fill 1, 0xeb000003;br+ CONST
+
+prog_imm:
+.fill 1, 0xed400000;ldil r6, CONST
+.fill 1, 0xed400002;ldih r6, CONST
+.ifill stw r6, 0(r3);0xe7b18000
+.ifill addi r3, r3, 4;0xe1198020
+
+prog_pop:
+.ifill subi r3, r3, 4;0xe1998020
+
+prog_xch:
+.ifill ldw r6, 0-4(r3);0xe731fffc
+.ifill ldw r7, 0-8(r3);0xe739fff8
+.ifill stw r6, 0-8(r3);0xe7b1fff8
+.ifill stw r7, 0-4(r3);0xe7b9fffc
+
+prog_not:
+.ifill ldw r6, 0-4(r3);0xe731fffc
+.ifill not r6;0xe4b7fffa
+.ifill stw r6, 0-4(r3);0xe7b1fffc
+
+.text
+main:
+ ;set address of input
+ ldil r1, inputdata@lo
+ ldih r1, inputdata@hi
+
+ ;set address of program start
+ ldil r2, prog_start@lo
+ ldih r2, prog_start@hi
+
+ ;set address to instruction table
+ ldil r3, instrtable@lo
+ ldih r3, instrtable@hi
+
+ ;set address to defer table
+ ldil r9, defertable@lo
+ ldih r9, defertable@hi
+
+
+ ;call jit compiler
+ call+ jit
+
+ ;set address to stack
+ ldil r3, stack@lo
+ ldih r3, stack@hi
+
+ ;make r15 a 0-register
+ ldis r15, 0
+ ;make r14 a 8-bit -1-register
+ ldis r14, 0xFF
+
+ ;call jit'ed prog
+ call+ prog_start
+
+ br+ main
+
+;first version only supports backward jumps
+jit:
+ ;r1 ... address to input, every byte is a new input
+ ; includes pc implicitly
+ ;r2 ... address to program start
+ ;r3 ... address of instruction table
+ ;r4 ... gets loaded with instr. prog. addr.
+ ;r5 ... input
+ ;r9 ... address to actual entry in defer table
+ ;r10... address to defer table
+
+ ;load address of program
+ ldil r13, prog_dup@lo
+ ldih r13, prog_dup@hi
+
+ ;load address of program
+ ldil r14, prog_mul@lo
+ ldih r14, prog_mul@hi
+
+ ldil r15, prog_consts@lo
+ ldih r15, prog_consts@hi
+
+ ;backup defer table address
+ mov r10, r9
+ ;decrement address to input by 1
+ subi r1, r1, 1
+
+vm_default:
+vm_loop:
+ ;increment input address
+ addi r1, r1, 1
+
+ ;store address of next instruction in table
+ stw r2, 0(r3)
+ ;increment instr. table
+ addi r3, r3, 4
+
+ ;load input
+ ldb r5, 0(r1)
+ ;we need to multiply input by 4 to get correct address offset
+ lls r0, r5, 2
+ ;calc position in jumptable
+ ldw r0, jumptable(r0)
+ ;jump to instr
+ brr r0
+
+vm_eof:
+ ;load address of program
+ ldil r4, prog_eof@lo
+ ldih r4, prog_eof@hi
+ ;program instruction (2)
+ ldw r0, 0(r4)
+ stx r0, 0(r2)
+ ldw r0, 4(r4)
+ stx r0, 4(r2)
+
+ ;end of program
+ ;now it is time to clear up the defer table
+
+ ldil r7, prog_jmp@lo
+ ldih r7, prog_jmp@hi
+ ;load branch template
+ ldw r7, 16(r7)
+
+ ;if actual and base are equal, no entry
+ cmp r9, r10
+ ;return
+ reteq-
+
+vm_defer:
+ ;load pointer to where to jump to
+ ldw r6, 0(r10)
+ ;load where to jump to
+ ldw r6, 0(r6)
+ ;load where to save from defer table
+ stw r8, 4(r10)
+
+ ;generate branch
+ sub r11, r6, r8
+ lrs r11, r11, 2
+ ;set the upper 16 bit 0
+ andx r11, 0xFFFF
+ ;shift to the position of imm in br
+ lls r11, r11, 7
+ or r6, r7, r11
+ stx r6, 0(r8)
+
+ addi r10, r10, 8
+ cmp r10, r9
+ reteq+
+ brnq- vm_defer
+
+;case *
+;42
+vm_mul:
+ ;program instruction (14)
+ ldw r0, 0(r14)
+ stx r0, 0(r2)
+ ldw r0, 4(r14)
+ stx r0, 4(r2)
+ ldw r0, 8(r14)
+ stx r0, 8(r2)
+ ldw r0, 12(r14)
+ stx r0, 12(r2)
+ ldw r0, 16(r14)
+ stx r0, 16(r2)
+ ldw r0, 20(r14)
+ stx r0, 20(r2)
+ ldw r0, 24(r14)
+ stx r0, 24(r2)
+ ldw r0, 28(r14)
+ stx r0, 28(r2)
+ ldw r0, 32(r14)
+ stx r0, 32(r2)
+ ldw r0, 36(r14)
+ stx r0, 36(r2)
+ ldw r0, 40(r14)
+ stx r0, 40(r2)
+ ldw r0, 44(r14)
+ stx r0, 44(r2)
+ ldw r0, 48(r14)
+ stx r0, 48(r2)
+ ldw r0, 52(r14)
+ stx r0, 52(r2)
+
+ ;increment address
+ addi r2, r2, 56
+
+ br+ vm_loop
+
+;case +
+;43
+vm_add:
+ ;load address of program
+ ldil r4, prog_add@lo
+ ldih r4, prog_add@hi
+
+ ;program instruction (5)
+ ldw r0, 0(r4)
+ stx r0, 0(r2)
+ ldw r0, 4(r4)
+ stx r0, 4(r2)
+ ldw r0, 8(r4)
+ stx r0, 8(r2)
+ ldw r0, 12(r4)
+ stx r0, 12(r2)
+ ldw r0, 16(r4)
+ stx r0, 16(r2)
+
+ ;increment address
+ addi r2, r2, 20
+
+ br+ vm_loop
+
+;case -
+;45
+vm_sub:
+ ;load address of program
+ ldil r4, prog_sub@lo
+ ldih r4, prog_sub@hi
+
+ ;program instruction (5)
+ ldw r0, 0(r4)
+ stx r0, 0(r2)
+ ldw r0, 4(r4)
+ stx r0, 4(r2)
+ ldw r0, 8(r4)
+ stx r0, 8(r2)
+ ldw r0, 12(r4)
+ stx r0, 12(r2)
+ ldw r0, 16(r4)
+ stx r0, 16(r2)
+
+ ;increment address
+ addi r2, r2, 20
+
+ br+ vm_loop
+
+;case 0 1 2 3 4 5 6 7 8 9
+;48-57
+vm_consts:
+ ;program instruction (3)
+ ldw r0, 0(r15)
+ ;the first instr. loads r6 with the number
+ ;thus we shall emulate this
+
+ ;call number
+ subi r6, r5, 48
+ ;shift 3 bits left, as the immediate in ldi has
+ ;an offset of 3
+ lls r6, r6, 3
+ ;now 'add' this to the ldi
+ or r0, r0, r6
+
+ ;store this 'dynamic' instruction
+ stx r0, 0(r2)
+ ldw r0, 4(r15)
+ stx r0, 4(r2)
+ ldw r0, 8(r15)
+ stx r0, 8(r2)
+
+ ;increment address
+ addi r2, r2, 12
+
+ br+ vm_loop
+
+;case <
+;60
+vm_lessthan:
+ ;load address of program
+ ldil r4, prog_lessthan@lo
+ ldih r4, prog_lessthan@hi
+
+ ;program instruction (6)
+ ldw r0, 0(r4)
+ stx r0, 0(r2)
+ ldw r0, 4(r4)
+ stx r0, 4(r2)
+ ldw r0, 8(r4)
+ stx r0, 8(r2)
+ ldw r0, 12(r4)
+ stx r0, 12(r2)
+ ldw r0, 16(r4)
+ stx r0, 16(r2)
+ ldw r0, 20(r4)
+ stx r0, 20(r2)
+
+ ;increment address
+ addi r2, r2, 24
+
+ br+ vm_loop
+
+;case D
+;68
+vm_dup:
+
+ ;program instruction (3)
+ ldw r0, 0(r13)
+ stx r0, 0(r2)
+ ldw r0, 4(r13)
+ stx r0, 4(r2)
+ ldw r0, 8(r13)
+ stx r0, 8(r2)
+
+ ;increment address
+ addi r2, r2, 12
+
+ br+ vm_loop
+
+;case I
+;73
+vm_imm:
+ ;the following instructions calculate the immediate
+ ;load new high byte
+ ldb r6, 4(r1)
+ ;shift high byte
+ lls r6, r6, 8
+ ;load 2nd byte
+ ldb r7, 3(r1)
+ ;add to high byte
+ add r6, r6, r7
+ ;shift
+ lls r6, r6, 8
+ ;load
+ ldb r7, 2(r1)
+ ;add
+ add r6, r6, r7
+ ;shift
+ lls r6, r6, 8
+ ;load
+ ldb r7, 1(r1)
+ ;add
+ add r6, r6, r7
+
+ ;now we will generate ldih/l which will store this
+ ;immediate into a register
+
+ ;load address of program
+ ldil r4, prog_imm@lo
+ ldih r4, prog_imm@hi
+
+ ;save r6 to r7
+ mov r7, r6
+
+ ;generate 1st instr
+ ldw r0, 0(r4)
+ andx r6, 0xFFFF
+ lls r6, r6, 3
+ or r0, r0, r6
+ stx r0, 0(r2)
+
+ ;generate 2nd instr
+ ldw r0, 4(r4)
+ andxh r7, 0xFFFF
+ lrs r7, r7, 13
+ or r0, r0, r7
+ stx r0, 4(r2)
+
+ ;now we program the instructions that will save the
+ ;immediate onto the stack and increment the later
+
+ ldw r0, 8(r4)
+ stx r0, 8(r2)
+ ldw r0, 12(r4)
+ stx r0, 12(r2)
+
+ ;increment address
+ addi r2, r2, 16
+
+ ;pc+4
+ addi r1, r1, 4
+ br+ vm_loop
+
+;case J
+;74
+vm_jmp:
+ ;gfreit mi net ...
+ ;gespeicherte instrs sollten input indepentent sein
+ ;jumptable verwenden
+ ;fuer forward jumps muss deferrer table gemacht werden *puke*
+
+ ;load address of program
+ ldil r4, prog_jmp@lo
+ ldih r4, prog_jmp@hi
+
+ ;program instruction (3)
+ ;decrement sp
+ ;subi r3, r3, 4
+ ldw r0, 0(r4)
+ stx r0, 0(r2)
+ ;load sp
+ ;ldw r6, 0(r3)
+ ldw r0, 4(r4)
+ stx r0, 4(r2)
+ ;compare to 0
+ ;cmpi r6,0
+ ldw r0, 8(r4)
+ stx r0, 8(r2)
+
+ ;breq+ vm_next
+ ;is statically known
+ ldw r0, 12(r4)
+ stx r0, 12(r2)
+
+ ;r8 has now the current base
+ ;ldw r8, 0-4(r3)
+ ;we add the offset to this instruction
+ addi r8, r2, 16
+
+
+ ;we know calculate the jump destination
+ ;set r6 to 0 (to clear upper bytes)
+ ldis r6, 0
+ ;load pc+1 input
+ ldb r6, 1(r1)
+ ;compare input with neg. max of 8 bit
+ cmpi r6, 0x80
+ brlt- vm_possign
+
+
+
+ ;generate negativ offset
+ ldis r7, 0xFF00
+ ;r6 is now the 'real' negativ number
+ or r6, r6, r7
+ ;todo: testing showed (at least once) we are off by 2 instr.
+ ;addi r6, r6, 2
+ ;multiply by to get the offset
+ lls r6, r6, 2
+ ;generate address in table
+ add r6, r3, r6
+ ;r0 now has the target address
+ ;todo: 0-4?
+ ldw r0, 0(r6)
+ ;we calc the offset
+ sub r8, r0, r8
+ ;we shift 2 bits out, because rel. br takes instr.
+ ;count and not address amount ...
+ lrs r8, r8, 2
+ ;set the upper 16 bit 0
+ andx r8, 0xFFFF
+ ;shift to the position of imm in br
+ lls r8, r8, 7
+ ;load template br
+ ldw r0, 16(r4)
+ or r0, r0, r8
+ stx r0, 16(r2)
+
+ ;increment address
+ addi r2, r2, 20
+
+ br+ vm_loop
+
+
+vm_possign:
+ ;we know save the address in the instrtable where the addr to jump to stands
+ ;the value doesn't exists at the moment, but it will at evaluation
+
+ ;save position to save the instr into defer table
+ stw r8, 4(r9)
+
+ ;todo: check if -1 is needed
+ ;subi r6, r6, 1
+ ;multiply with 2 to get offset right
+ lls r6, r6, 2
+ ;add to current base
+ add r6, r3, r6
+ ;save the address to defer table
+ stw r6, 0(r9)
+ ;increment defer table address
+ addi r9, r9, 8
+ ;increment address
+ addi r2, r2, 20
+ br+ vm_loop
+
+;case P
+;80
+vm_pop:
+ ;load address of program
+ ldil r4, prog_pop@lo
+ ldih r4, prog_pop@hi
+
+ ;program instruction (1)
+ ldw r0, 0(r4)
+ stx r0, 0(r2)
+
+ ;increment address
+ addi r2, r2, 4
+
+ br+ vm_loop
+
+;case X
+;88
+vm_xch:
+ ;load address of program
+ ldil r4, prog_xch@lo
+ ldih r4, prog_xch@hi
+
+ ;program instruction (4)
+ ldw r0, 0(r4)
+ stx r0, 0(r2)
+ ldw r0, 4(r4)
+ stx r0, 4(r2)
+ ldw r0, 8(r4)
+ stx r0, 8(r2)
+ ldw r0, 12(r4)
+ stx r0, 12(r2)
+
+ ;increment address
+ addi r2, r2, 16
+
+ br+ vm_loop
+
+;case ~
+;126
+vm_not:
+ ;load address of program
+ ldil r4, prog_not@lo
+ ldih r4, prog_not@hi
+
+ ;program instruction (3)
+ ldw r0, 0(r4)
+ stx r0, 0(r2)
+ ldw r0, 4(r4)
+ stx r0, 4(r2)
+ ldw r0, 8(r4)
+ stx r0, 8(r2)
+
+ ;increment address
+ addi r2, r2, 12
+
+ br+ vm_loop
+
+prog_start:
+
+.data
+jumptable:
+;0
+.fill 1, vm_eof
+.fill 41, vm_default
+;42
+.fill 1, vm_mul
+;43
+.fill 1, vm_add
+;44
+.fill 1, vm_default
+;45
+.fill 1, vm_sub
+;46-47
+.fill 2, vm_default
+;48-57
+.fill 10, vm_consts
+;58-59
+.fill 2, vm_default
+;60
+.fill 1, vm_lessthan
+;61-67
+.fill 7, vm_default
+;68
+.fill 1, vm_dup
+;69-72
+.fill 4, vm_default
+;73
+.fill 1, vm_imm
+;74
+.fill 1, vm_jmp
+;75-79
+.fill 5, vm_default
+;80
+.fill 1, vm_pop
+;81-87
+.fill 7, vm_default
+;88
+.fill 1, vm_xch
+;89-125
+.fill 37, vm_default
+;126
+.fill 1, vm_not
+;127-255
+.fill 129, vm_default
+
+;we assume not more than 3 entries
+defertable:
+.fill 6, 0
--- /dev/null
+../8_benchs/src/vm.s
\ No newline at end of file
updateDisable :: Parser Word32
updateDisable = do { char 'd'; return 1} <|> do {string ""; return 0}
+highonly :: Parser Word32
+highonly = do { char 'h'; return 1} <|> do {string ""; return 0}
+
highlow :: Parser Word32
highlow = do { char 'h'; return 1} <|> do {char 'l'; return 0} <|> do {string ""; return 0}
csv2i_cd dict f = f<$>carry<*>updateDisable<*>condition<%>reg<.>reg<.>(iLit5 dict)
csv2i_d dict f = f<$>updateDisable<*>condition<%>reg<.>reg<.>(iLit5 dict)
csv2i_scd dict f = f<$>sign<*>carry<*>updateDisable<*>condition<%>reg<.>reg<.>(iLit12 dict)
-csv2i_sl dict f = f<$>sign<*>highlow<*>condition<%>reg<.>(iLit16 dict)
+csv2i_sl dict f = f<$>highonly<*>sign<*>condition<%>reg<.>(iLit16 dict)
+csv2i_sl' dict f = f<$>sign<*>condition<%>reg<.>(iLit16 dict)
csv2i_lfd dict f = f<$>highlow<*>fill<*>updateDisable<*>condition<%>reg<.>(iLit16 dict)
csv3_cd f = f<$>carry<*>updateDisable<*>condition<%>reg<.>reg<.>reg
csv3_d f = f<$>updateDisable<*>condition<%>reg<.>reg<.>reg
lls, lrs, ars,
pop, push, disc, fetch,
movpf, movsf, movpt, movst,
- ldh, ldb, ldw, ldi,
+ ldh, ldb, ldw, ldi, ldil,
stw, sth, stb,
ldx, stx,
br, ret, call, reti,
ldh dict = ins "ldh" (csv2m dict) $ mformi 0x10
ldb dict = ins "ldb" (csv2m dict) $ mformi 0x12
ldi dict = ins "ldi" (csv2i_sl dict) $ lformi' 0x1a
+ldil dict = ins "ldil" (csv2i_sl' dict) $ lformi' 0x1a 0
stw dict = ins "stw" (csv2m dict) $ mformi 0x0f
sth dict = ins "sth" (csv2m dict) $ mformi 0x11
stb dict = ins "stb" (csv2m dict) $ mformi 0x13
aformi' opcd s c d cond rd ra = aformi opcd s c d cond rd ra 0
lformi opcd hl f d cond rd imm = pack [(cond,28),(opcd,23),(rd,19),(imm,3),(hl,2),(f,1),(d,0)]
-lformi' opcd s hl cond rd imm = lformi opcd s hl 0 cond rd imm
-lformi'not opcd cond rd = lformi opcd 0 1 0 cond rd 0xefffffff
+lformi' opcd hl s cond rd imm = lformi opcd s hl 0 cond rd imm
+lformi'not opcd cond rd = lformi opcd 0 1 0 cond rd 0xffff
mformi opcd cond rd disp ra = pack [(cond,28),(opcd,23),(rd,19),(ra,15),(disp,0)]
mformi' opcd cond rd = mformi opcd cond rd 0
shiform opcd lr a c d cond rd ra imm = pack [(cond,28),(opcd,23),(rd,19),(ra,15),(imm,10),(lr,3),(a,2),(c,1),(d,0)]
--- ppc64 stuff (TODO: remove)
-iform opcd aa lk li = pack [(opcd,6),(li,30),(aa,31),(lk,0)]
-scform opcd lev = pack [(opcd,6),(lev,27),(1,31)]
-dform'b opcd bf l ra si = pack [(opcd,6),(bf,9),(0,10),(l,11),(ra,16),(si,0)]
-dsform opcd rt ra ds xo = pack [(opcd,6),(rt,11),(ra,16),(ds,30),(xo,0)]
-xform'a opcd rt ra rb xo = pack [(opcd,6),(rt,11),(ra,16),(rb,21),(xo,31)]
-xform'b opcd xo bf l ra rb = pack [(opcd,6),(bf,9),(0,10),(l,11),(ra,16),(rb,21),(xo,31),(0,0)]
-xform'c opcd xo rs ra rb rc = pack [(opcd,6),(rs,11),(ra,16),(rb,21),(xo,31),(rc,0)]
-xform'd opcd xo rc rs ra = pack [(opcd,6),(rs,11),(ra,16),(0,21),(xo,31),(rc,0)]
-xlform'a opcd xo bt ba bb = pack [(opcd,6),(bt,11),(ba,16),(bb,21),(xo,31)]
-xlform'b opcd xo lk bo bi bh = pack [(opcd,6),(bo,11),(bi,16),(bh,21),(xo,31),(lk,0)]
-xlform'c opcd xo bf bfa = pack [(opcd,6),(bf,9),(bfa,14),(xo,31)]
-xfxform opcd xo rs spr = pack [(opcd,6),(rs,11),(spr,21),(xo,31)]
-xfxform'b opcd h xo fxm rs = pack [(opcd,6),(rs,11),(h,12),(fxm,20),(xo,31)]
---xflform
--- fix xsform
-xsform opcd xo rc ra rs sh = pack [(opcd,6),(rs,11),(ra,16),(sh,21),(xo,30),(sh,31),(rc,0)]
-xoform' opcd xo oe rc rt ra = pack [(opcd,6),(rt,11),(ra,16),(0,21),(oe,22),(xo,31),(rc,0)]
---aform
-mform opcd rc ra rs sh mb me = pack [(opcd,6),(rs,11),(ra,16),(sh,21),(mb,26),(me,31),(rc,0)]
--- mdform needs to be fixed to handle sh correctly
-mdform opcd h rc ra rs sh mb = pack [(opcd,6),(rs,11),(ra,16),(sh,21),(mb,27),(h,30),(sh,31),(rc,0)]
-mdsform opcd h rc ra rs rb mb = pack [(opcd,6),(rs,11),(ra,16),(rb,21),(mb,27),(h,31),(rc,0)]
-
-- bit-packing --
pack bf = foldr1 (.|.) $ map (uncurry rotateL) bf
parseDTFLine :: [DictElem] -> Parser DTF
parseDTFLine dict = foldl1 (<|>) (fmap (\x -> try (x dict)) lineFormats) <* char '\n'
-lineFormats = [lf_define, lf_sdata, lf_stext, lf_org, lf_data, lf_comment, lf_toparse, lf_label]
+lineFormats = [lf_define, lf_sdata, lf_stext, lf_org, lf_data, lf_ifill, lf_comment, lf_toparse, lf_label]
-- helper
parseIdent :: Parser String
repeat <- try (do {size <- many1 $ noneOf "\n;,"; char ','; return $ size}) <|> return "1"
-- TODO: atm 32bit imm only
code <- many1 $ noneOf "\n;"
- -- TODO: this is quite ugly here :/
- let (Right val) = parse (parseConst d) "" code
- let (Right r) = parse (parseConst d) "" repeat
+ let val = case parse (parseConst d) "" code of
+ Right v -> v
+ Left err -> error $ show err
+ let r = case parse (parseConst d) "" repeat of
+ Right v -> v
+ Left err -> error $ show err
comment <- try(parseComment) <|> parseMySpaces
return $ DTF_Fill r val (fill ++ (if repeat == "1" then "" else repeat) ++ code) l comment
+lf_ifill d = do
+ l <- try (parseLabel) <|> string ""
+ skipMany space
+ fill <- string ".ifill "
+ code <- many1 $ noneOf "\n;"
+ let val = case parse (instruction (0,d)) "" (code++"\n") of
+ Right v -> v
+ Left err -> error $ show err
+ comment <- try(parseComment) <|> parseMySpaces
+ return $ DTF_Fill 1 val (fill ++ code) l comment
+
lf_comment _ = do
comment <- parseComment
return $ DTF_Comment comment
bool ignoreBreak = false;
+bool exitProg = false;
+
void doExit(const vector<string>&)
{
- exit(EXIT_SUCCESS);
+ exitProg = true;
}
unsigned int convertStringToNum(const std::string& in)
Func lastFunc = NULL;
- while(1) {
+ while(!exitProg) {
UserInput = Reader.GetLine("> ", Tokens, EndOfInput);
if(EndOfInput) {
break;
}
else {
stringstream err;
- err << "opcode not found" << endl;
+ err << "opcode not found. in was " << opcode << endl;
throw err.str();
}
}
if(m_d) op << 'D';
if(m_c) op << 'C';
- op << " r" << m_rd << ", r" << m_ra << ", r" << m_rb;
+ op << this->getConditionFlag() << " r" << m_rd << ", r" << m_ra << ", r" << m_rb;
return op.str();
}
{
CDat val = this->m_cpu->getRegister(this->m_rd);
CDat imm = generate16ImmFill(this->m_imm);
+ if(this->m_hl) {
+ imm <<= 16;
+ }
val &= imm;
this->m_cpu->setRegister(this->m_rd, val);
dynamic_bitset<> immb = argbits;
immb.resize(16);
- this->m_imm = this->generate16ImmSign(immb.to_ulong());
+ this->m_imm = this->generate16ImmSign(immb.to_ulong())*4;
}
this->m_cpu->setRAM(sp, this->m_cpu->getNextPC());
this->m_cpu->setStack(sp);
}
+ /* fall through */
case 0:
- this->m_cpu->setNextPC(pc+this->m_imm);
+ this->m_cpu->setNextPC(pc+(this->m_imm));
break;
case 2:
case 3:
op << this->getConditionFlag() << (m_taken ? '+' : '-');
if(m_typ < 2) {
- op << " 0x" << std::hex << m_imm << "(" << std::dec << m_imm << ")";
+ op << " 0x" << std::hex << m_imm << "(" << std::dec << m_imm << ", " << (int) m_imm << ")";
}
return op.str();
}
int8_t op = insns[pc];
int32_t t;
+ printf("pc: %d op: %c\n", pc, op);
/* putchar(op); */
/* printf(" %d/%d:\t%08x\t%08x\t%08x\t%08x\t%08x\t%08x\t%08x\t%08x\n", */
--- /dev/null
+.data
+.org 0x10
+inputdata:
+;8 * 8 4
+.fill 1, 0x382A3834
+;1 X * 8
+.fill 1, 0x31582A38
+;+ D X -
+.fill 1, 0x2B44582D
+;P \xF8 J D
+.fill 1, 0x50F84A44
+;+ * 8 6
+.fill 1, 0x2B2A3836
+;\000 \020 I D
+.fill 1, 0x00204944
+;~ < \000 \000
+.fill 1, 0x7E3C0000
+;8 P \005 J
+.fill 1, 0x3850054A
+;* 8
+.fill 1, 0x2A38
+
+stack:
+.fill 256, 0
+
+.text
+main:
+ ;set address of input
+ ldil r1, inputdata@lo
+ ldih r1, inputdata@hi
+
+ call+ vm
+ br+ main
+
+vm:
+ ;r0 ... lut address (can be overwritten)
+ ;r1 ... address to input, every byte is a new input
+ ; includes pc implicitly
+ ;r3 ... effective stack address
+ ;r5 ... input
+
+ ;decrement address to input by 1
+ subi r1, r1, 1
+ ;load base address of stack
+ ldil r3, stack@lo
+ ldih r3, stack@hi
+
+vm_default:
+vm_loop:
+ ;increment input address
+ addi r1, r1, 1
+ ;load input
+ ldb r5, 0(r1)
+ ;we need to multiply input by 4 to get correct address offset
+ lls r0, r5, 2
+ ;calc position in jumptable
+ ldw r0, jumptable(r0)
+ ;jump to instr
+ brr r0
+
+vm_eof:
+ ;load stack[sp-1]
+ ldw r0, 0-4(r3);
+ ret+;
+
+;case *
+;42
+vm_mul:
+ ;decrement sp
+ subi r3, r3, 4
+ ;load sp
+ ldw r6, 0(r3)
+ ;load sp-1
+ ldw r7, 0-4(r3)
+
+ ;return init
+ ldis r8, 0
+ ;save of sp-1
+ mov r0, r7
+ ;check if sp-1 is even or odd
+ andx r0, 1
+ ;add sp to result
+ adddnz r8, r8, r6
+ ;if odd decrement sp-1
+ subinz r7, r7, 1
+ ;just to get zero flag unset
+ addizs r7, r7, 0
+loop:
+ ;if last was not zero
+ ;add to sp-1 to result
+ adddnz r8, r8, r6
+ adddnz r8, r8, r6
+ ;decrement sp-1 by 2
+ subi r7, r7, 2
+ ;jump if not zero
+ brnz+ loop
+ ;save result
+ stw r8, 0-4(r3)
+ br+ vm_loop
+
+;case +
+;43
+vm_add:
+ ;decrement sp
+ subi r3, r3, 4
+ ;load sp
+ ldw r6, 0(r3)
+ ;load sp-1
+ ldw r7, 0-4(r3)
+ ;sp-1 = sp-1 + sp
+ add r7, r7, r6
+ ;store sp-1
+ stw r7, 0-4(r3)
+ br+ vm_loop
+
+;case -
+;45
+vm_sub:
+ ;decrement sp
+ subi r3, r3, 4
+ ;load sp
+ ldw r6, 0(r3)
+ ;load sp-1
+ ldw r7, 0-4(r3)
+ ;sp-1 = sp-1 - sp
+ sub r7, r7, r6
+ ;store sp-1
+ stw r7, 0-4(r3)
+ br+ vm_loop
+
+;case 0 1 2 3 4 5 6 7 8 9
+;48-57
+vm_consts:
+ ;input minus offset
+ subi r6, r5, 48
+ ;store onto stack
+ stw r6, 0(r3)
+ ;increment stack addr
+ addi r3, r3, 4
+ br+ vm_loop
+
+;case <
+;60
+vm_lessthan:
+ ;decrement sp
+ subi r3, r3, 4
+ ;load sp
+ ldw r6, 0(r3)
+ ;load sp-1
+ ldw r7, 0-4(r3)
+ ;load r8 with 0
+ ldis r8, 0
+ ;compare sp-1 with sp
+ cmp r7, r6
+ ;set r8 to -1 if less than
+ ldislt r8, 0xFF
+ ;store r8 to sp-1
+ stw r8, 0-4(r3)
+ br+ vm_loop
+
+;case D
+;68
+vm_dup:
+ ;load sp-1
+ ldw r6, 0-4(r3)
+ ;store to sp
+ stw r6, 0(r3)
+ ;increment stack addr
+ addi r3, r3, 4
+ br+ vm_loop
+
+;case I
+;73
+vm_imm:
+ ;load new high byte
+ ldb r6, 4(r1)
+ ;shift high byte
+ lls r6, r6, 8
+ ;load 2nd byte
+ ldb r7, 3(r1)
+ ;add to high byte
+ add r6, r6, r7
+ ;shift
+ lls r6, r6, 8
+ ;load
+ ldb r7, 2(r1)
+ ;add
+ add r6, r6, r7
+ ;shift
+ lls r6, r6, 8
+ ;load
+ ldb r7, 1(r1)
+ ;add
+ add r6, r6, r7
+ ;store result to stack
+ stw r6, 0(r3)
+ ;pc+4
+ addi r1, r1, 4
+ ;increment sp
+ addi r3, r3, 4
+ br+ vm_loop
+
+;case J
+;74
+vm_jmp:
+ ;decrement sp
+ subi r3, r3, 4
+ ;load sp
+ ldw r6, 0(r3)
+ ;compare to 0
+ cmpi r6,0
+ ;increment pc if == 0
+ addideq r1, r1, 1
+ breq+ vm_loop
+ ;if != 0
+ ;set r6 to 0 (to clear upper bytes)
+ ldis r6, 0
+ ;load pc+1 input
+ ldb r6, 1(r1)
+ ;compare input with neg. max of 8 bit
+ cmpi r6, 0x80
+ brlt- vm_possign
+ ldis r7, 0xFF00
+ add r6, r6, r7
+vm_possign:
+ ;pc += data
+ add r1, r1, r6
+ br+ vm_loop
+
+;case P
+;80
+vm_pop:
+ ;decrement stack addr
+ subi r3, r3, 4
+ br+ vm_loop
+
+;case X
+;88
+vm_xch:
+ ;load sp-1
+ ldw r6, 0-4(r3)
+ ;load sp-2
+ ldw r7, 0-8(r3)
+ ;store sp-1 to sp-2
+ stw r6, 0-8(r3)
+ ;store sp-2 to sp-1
+ stw r7, 0-4(r3)
+ br+ vm_loop
+
+;case ~
+;126
+vm_not:
+ ldw r6, 0-4(r3)
+ not r6
+ stw r6, 0-4(r3)
+ br+ vm_loop
+
+.data
+jumptable:
+;0
+.fill 1, vm_eof
+.fill 41, vm_default
+;42
+.fill 1, vm_mul
+;43
+.fill 1, vm_add
+;44
+.fill 1, vm_default
+;45
+.fill 1, vm_sub
+;46-47
+.fill 2, vm_default
+;48-57
+.fill 10, vm_consts
+;58-59
+.fill 2, vm_default
+;60
+.fill 1, vm_lessthan
+;61-67
+.fill 7, vm_default
+;68
+.fill 1, vm_dup
+;69-72
+.fill 4, vm_default
+;73
+.fill 1, vm_imm
+;74
+.fill 1, vm_jmp
+;75-79
+.fill 5, vm_default
+;80
+.fill 1, vm_pop
+;81-87
+.fill 7, vm_default
+;88
+.fill 1, vm_xch
+;89-125
+.fill 37, vm_default
+;126
+.fill 1, vm_not
+;127-255
+.fill 129, vm_default
projects / calu.git / commitdiff