--- /dev/null
+transcript
--- /dev/null
+.text
+ ldi r5, 0x5a
+ ldi r0, 0x100b
+ stw r5, 0(r0)
--- /dev/null
+pwd
+# /home/stefan/processor/calu/3a_asm
+cd ..
+cd cpu/sim
+# reading modelsim.ini
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package mem_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package common_pkg
+# -- Compiling package body common_pkg
+# -- Loading package common_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package core_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_uart_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_7seg_pkg
+# -- Compiling package body extension_7seg_pkg
+# -- Loading package extension_7seg_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of extension_7seg
+# -- Loading entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture beh of rs232_tx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav of decode_stage
+# -- Loading entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package alu_pkg
+# -- Compiling package body alu_pkg
+# -- Loading package alu_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture add_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture and_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture or_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture xor_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture shift_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity alu
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behaviour of alu
+# -- Loading entity alu
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of extension_gpm
+# -- Loading entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behav of execute_stage
+# -- Loading entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling entity writeback_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of writeback_stage
+# -- Loading entity writeback_stage
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity pipeline_tb
+# -- Compiling architecture behavior of pipeline_tb
+# -- Compiling configuration pipeline_conf_beh
+# -- Loading entity pipeline_tb
+# -- Loading architecture behavior of pipeline_tb
+# -- Loading entity fetch_stage
+# -- Loading entity decode_stage
+# -- Loading package alu_pkg
+# -- Loading entity execute_stage
+# -- Loading entity writeback_stage
+# vsim -t ns work.pipeline_conf_beh
+# Loading std.standard
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.common_pkg(body)
+# Loading work.extension_pkg
+# Loading work.core_pkg
+# Loading work.alu_pkg(body)
+# Loading work.pipeline_conf_beh
+# Loading work.pipeline_tb(behavior)
+# Loading work.mem_pkg
+# Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
+# Loading work.rom(behaviour)
+# Loading work.decode_stage(behav)
+# Loading work.r2_w_ram(behaviour)
+# Loading work.decoder(behav_d)
+# Loading work.execute_stage(behav)
+# Loading work.alu(behaviour)
+# Loading work.exec_op(add_op)
+# Loading work.exec_op(and_op)
+# Loading work.exec_op(or_op)
+# Loading work.exec_op(xor_op)
+# Loading work.exec_op(shift_op)
+# Loading work.extension_gpm(behav)
+# Loading work.extension_uart_pkg
+# Loading work.extension_7seg_pkg(body)
+# Loading work.writeback_stage(behav)
+# Loading work.r_w_ram_be(behaviour)
+# Loading work.extension_uart(behav)
+# Loading ieee.std_logic_arith(body)
+# Loading ieee.std_logic_unsigned(body)
+# Loading work.rs232_tx(beh)
+# Loading work.rs232_rx(beh)
+# Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 3 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 4 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 5 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Fatal: (vsim-3420) Array lengths do not match. Left is 32 (31 downto 0). Right is 31 (31 downto 1).
+# Time: 20 ns Iteration: 1 Process: /pipeline_tb/fetch_st/instruction_rom/line__13 File: ../src/rom_b.vhd
+# Fatal error in Process line__13 at ../src/rom_b.vhd line 127
+#
+# HDL call sequence:
+# Stopped at ../src/rom_b.vhd 127 Process line__13
+#
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package mem_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package common_pkg
+# -- Compiling package body common_pkg
+# -- Loading package common_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package core_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_uart_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_7seg_pkg
+# -- Compiling package body extension_7seg_pkg
+# -- Loading package extension_7seg_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of extension_7seg
+# -- Loading entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture beh of rs232_tx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav of decode_stage
+# -- Loading entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package alu_pkg
+# -- Compiling package body alu_pkg
+# -- Loading package alu_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture add_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture and_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture or_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture xor_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture shift_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity alu
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behaviour of alu
+# -- Loading entity alu
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of extension_gpm
+# -- Loading entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behav of execute_stage
+# -- Loading entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling entity writeback_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of writeback_stage
+# -- Loading entity writeback_stage
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity pipeline_tb
+# -- Compiling architecture behavior of pipeline_tb
+# -- Compiling configuration pipeline_conf_beh
+# -- Loading entity pipeline_tb
+# -- Loading architecture behavior of pipeline_tb
+# -- Loading entity fetch_stage
+# -- Loading entity decode_stage
+# -- Loading package alu_pkg
+# -- Loading entity execute_stage
+# -- Loading entity writeback_stage
+# vsim -t ns work.pipeline_conf_beh
+# Loading std.standard
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.common_pkg(body)
+# Loading work.extension_pkg
+# Loading work.core_pkg
+# Loading work.alu_pkg(body)
+# Loading work.pipeline_conf_beh
+# Loading work.pipeline_tb(behavior)
+# Loading work.mem_pkg
+# Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
+# Loading work.rom(behaviour)
+# Loading work.decode_stage(behav)
+# Loading work.r2_w_ram(behaviour)
+# Loading work.decoder(behav_d)
+# Loading work.execute_stage(behav)
+# Loading work.alu(behaviour)
+# Loading work.exec_op(add_op)
+# Loading work.exec_op(and_op)
+# Loading work.exec_op(or_op)
+# Loading work.exec_op(xor_op)
+# Loading work.exec_op(shift_op)
+# Loading work.extension_gpm(behav)
+# Loading work.extension_uart_pkg
+# Loading work.extension_7seg_pkg(body)
+# Loading work.writeback_stage(behav)
+# Loading work.r_w_ram_be(behaviour)
+# Loading work.extension_uart(behav)
+# Loading ieee.std_logic_arith(body)
+# Loading ieee.std_logic_unsigned(body)
+# Loading work.rs232_tx(beh)
+# Loading work.rs232_rx(beh)
+# Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 3 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 4 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 5 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 20 ns Iteration: 1 Instance: /pipeline_tb/writeback_st/data_ram
+# WARNING: No extended dataflow License exists
+run
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package mem_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package common_pkg
+# -- Compiling package body common_pkg
+# -- Loading package common_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package core_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_uart_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_7seg_pkg
+# -- Compiling package body extension_7seg_pkg
+# -- Loading package extension_7seg_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of extension_7seg
+# -- Loading entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture beh of rs232_tx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav of decode_stage
+# -- Loading entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package alu_pkg
+# -- Compiling package body alu_pkg
+# -- Loading package alu_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture add_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture and_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture or_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture xor_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture shift_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity alu
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behaviour of alu
+# -- Loading entity alu
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of extension_gpm
+# -- Loading entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behav of execute_stage
+# -- Loading entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling entity writeback_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of writeback_stage
+# -- Loading entity writeback_stage
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity pipeline_tb
+# -- Compiling architecture behavior of pipeline_tb
+# -- Compiling configuration pipeline_conf_beh
+# -- Loading entity pipeline_tb
+# -- Loading architecture behavior of pipeline_tb
+# -- Loading entity fetch_stage
+# -- Loading entity decode_stage
+# -- Loading package alu_pkg
+# -- Loading entity execute_stage
+# -- Loading entity writeback_stage
+# vsim -t ns work.pipeline_conf_beh
+# Loading std.standard
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.common_pkg(body)
+# Loading work.extension_pkg
+# Loading work.core_pkg
+# Loading work.alu_pkg(body)
+# Loading work.pipeline_conf_beh
+# Loading work.pipeline_tb(behavior)
+# Loading work.mem_pkg
+# Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
+# Loading work.rom(behaviour)
+# Loading work.decode_stage(behav)
+# Loading work.r2_w_ram(behaviour)
+# Loading work.decoder(behav_d)
+# Loading work.execute_stage(behav)
+# Loading work.alu(behaviour)
+# Loading work.exec_op(add_op)
+# Loading work.exec_op(and_op)
+# Loading work.exec_op(or_op)
+# Loading work.exec_op(xor_op)
+# Loading work.exec_op(shift_op)
+# Loading work.extension_gpm(behav)
+# Loading work.extension_uart_pkg
+# Loading work.extension_7seg_pkg(body)
+# Loading work.writeback_stage(behav)
+# Loading work.r_w_ram_be(behaviour)
+# Loading work.extension_uart(behav)
+# Loading ieee.std_logic_arith(body)
+# Loading ieee.std_logic_unsigned(body)
+# Loading work.rs232_tx(beh)
+# Loading work.rs232_rx(beh)
+# Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 3 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 4 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 5 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 20 ns Iteration: 1 Instance: /pipeline_tb/writeback_st/data_ram
+run
+restart
+run
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 3 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 4 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 5 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 20 ns Iteration: 1 Instance: /pipeline_tb/writeback_st/data_ram
+run
+vcom -reportprogress 300 -work work /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# ** Error: /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd(106): Illegal target for signal assignment.
+# ** Error: /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd(106): (vcom-1136) Unknown identifier "instr_rd_addr_nxt".
+# ** Error: /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd(121): VHDL Compiler exiting
+vcom -reportprogress 300 -work work /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+vcom -reportprogress 300 -work work /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+restart
+# Loading work.fetch_stage(behav)
+run
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 3 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 4 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 5 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 20 ns Iteration: 1 Instance: /pipeline_tb/writeback_st/data_ram
+run
+vcom -reportprogress 300 -work work /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+restart
+# Loading work.fetch_stage(behav)
+run
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 3 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 4 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 5 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 20 ns Iteration: 1 Instance: /pipeline_tb/writeback_st/data_ram
+run
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package mem_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package common_pkg
+# -- Compiling package body common_pkg
+# -- Loading package common_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package core_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_uart_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_7seg_pkg
+# -- Compiling package body extension_7seg_pkg
+# -- Loading package extension_7seg_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of extension_7seg
+# -- Loading entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture beh of rs232_tx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav of decode_stage
+# -- Loading entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package alu_pkg
+# -- Compiling package body alu_pkg
+# -- Loading package alu_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture add_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture and_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture or_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture xor_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture shift_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity alu
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behaviour of alu
+# -- Loading entity alu
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of extension_gpm
+# -- Loading entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behav of execute_stage
+# -- Loading entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling entity writeback_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of writeback_stage
+# -- Loading entity writeback_stage
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity pipeline_tb
+# -- Compiling architecture behavior of pipeline_tb
+# -- Compiling configuration pipeline_conf_beh
+# -- Loading entity pipeline_tb
+# -- Loading architecture behavior of pipeline_tb
+# -- Loading entity fetch_stage
+# -- Loading entity decode_stage
+# -- Loading package alu_pkg
+# -- Loading entity execute_stage
+# -- Loading entity writeback_stage
+# vsim -t ns work.pipeline_conf_beh
+# Loading std.standard
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.common_pkg(body)
+# Loading work.extension_pkg
+# Loading work.core_pkg
+# Loading work.alu_pkg(body)
+# Loading work.pipeline_conf_beh
+# Loading work.pipeline_tb(behavior)
+# Loading work.mem_pkg
+# Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
+# Loading work.rom(behaviour)
+# Loading work.decode_stage(behav)
+# Loading work.r2_w_ram(behaviour)
+# Loading work.decoder(behav_d)
+# Loading work.execute_stage(behav)
+# Loading work.alu(behaviour)
+# Loading work.exec_op(add_op)
+# Loading work.exec_op(and_op)
+# Loading work.exec_op(or_op)
+# Loading work.exec_op(xor_op)
+# Loading work.exec_op(shift_op)
+# Loading work.extension_gpm(behav)
+# Loading work.extension_uart_pkg
+# Loading work.extension_7seg_pkg(body)
+# Loading work.writeback_stage(behav)
+# Loading work.r_w_ram_be(behaviour)
+# Loading work.extension_uart(behav)
+# Loading ieee.std_logic_arith(body)
+# Loading ieee.std_logic_unsigned(body)
+# Loading work.rs232_tx(beh)
+# Loading work.rs232_rx(beh)
+# Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 3 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 4 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 5 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 20 ns Iteration: 1 Instance: /pipeline_tb/writeback_st/data_ram
+run
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package mem_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package common_pkg
+# -- Compiling package body common_pkg
+# -- Loading package common_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package core_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_uart_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_7seg_pkg
+# -- Compiling package body extension_7seg_pkg
+# -- Loading package extension_7seg_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of extension_7seg
+# -- Loading entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture beh of rs232_tx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav of decode_stage
+# -- Loading entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package alu_pkg
+# -- Compiling package body alu_pkg
+# -- Loading package alu_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture add_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture and_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture or_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture xor_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture shift_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity alu
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behaviour of alu
+# -- Loading entity alu
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of extension_gpm
+# -- Loading entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behav of execute_stage
+# -- Loading entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling entity writeback_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of writeback_stage
+# -- Loading entity writeback_stage
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity pipeline_tb
+# -- Compiling architecture behavior of pipeline_tb
+# -- Compiling configuration pipeline_conf_beh
+# -- Loading entity pipeline_tb
+# -- Loading architecture behavior of pipeline_tb
+# -- Loading entity fetch_stage
+# -- Loading entity decode_stage
+# -- Loading package alu_pkg
+# -- Loading entity execute_stage
+# -- Loading entity writeback_stage
+# vsim -t ns work.pipeline_conf_beh
+# Loading std.standard
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.common_pkg(body)
+# Loading work.extension_pkg
+# Loading work.core_pkg
+# Loading work.alu_pkg(body)
+# Loading work.pipeline_conf_beh
+# Loading work.pipeline_tb(behavior)
+# Loading work.mem_pkg
+# Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
+# Loading work.rom(behaviour)
+# Loading work.decode_stage(behav)
+# Loading work.r2_w_ram(behaviour)
+# Loading work.decoder(behav_d)
+# Loading work.execute_stage(behav)
+# Loading work.alu(behaviour)
+# Loading work.exec_op(add_op)
+# Loading work.exec_op(and_op)
+# Loading work.exec_op(or_op)
+# Loading work.exec_op(xor_op)
+# Loading work.exec_op(shift_op)
+# Loading work.extension_gpm(behav)
+# Loading work.extension_uart_pkg
+# Loading work.extension_7seg_pkg(body)
+# Loading work.writeback_stage(behav)
+# Loading work.r_w_ram_be(behaviour)
+# Loading work.extension_uart(behav)
+# Loading ieee.std_logic_arith(body)
+# Loading ieee.std_logic_unsigned(body)
+# Loading work.rs232_tx(beh)
+# Loading work.rs232_rx(beh)
+# Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 3 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 4 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 5 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 20 ns Iteration: 1 Instance: /pipeline_tb/writeback_st/data_ram
+run
+run
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package mem_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package common_pkg
+# -- Compiling package body common_pkg
+# -- Loading package common_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package core_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_uart_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_7seg_pkg
+# -- Compiling package body extension_7seg_pkg
+# -- Loading package extension_7seg_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of extension_7seg
+# -- Loading entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture beh of rs232_tx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav of decode_stage
+# -- Loading entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package alu_pkg
+# -- Compiling package body alu_pkg
+# -- Loading package alu_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture add_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture and_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture or_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture xor_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture shift_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity alu
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behaviour of alu
+# -- Loading entity alu
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of extension_gpm
+# -- Loading entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behav of execute_stage
+# -- Loading entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling entity writeback_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of writeback_stage
+# -- Loading entity writeback_stage
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity pipeline_tb
+# -- Compiling architecture behavior of pipeline_tb
+# -- Compiling configuration pipeline_conf_beh
+# -- Loading entity pipeline_tb
+# -- Loading architecture behavior of pipeline_tb
+# -- Loading entity fetch_stage
+# -- Loading entity decode_stage
+# -- Loading package alu_pkg
+# -- Loading entity execute_stage
+# -- Loading entity writeback_stage
+# vsim -t ns work.pipeline_conf_beh
+# Loading std.standard
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.common_pkg(body)
+# Loading work.extension_pkg
+# Loading work.core_pkg
+# Loading work.alu_pkg(body)
+# Loading work.pipeline_conf_beh
+# Loading work.pipeline_tb(behavior)
+# Loading work.mem_pkg
+# Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
+# Loading work.rom(behaviour)
+# Loading work.decode_stage(behav)
+# Loading work.r2_w_ram(behaviour)
+# Loading work.decoder(behav_d)
+# Loading work.execute_stage(behav)
+# Loading work.alu(behaviour)
+# Loading work.exec_op(add_op)
+# Loading work.exec_op(and_op)
+# Loading work.exec_op(or_op)
+# Loading work.exec_op(xor_op)
+# Loading work.exec_op(shift_op)
+# Loading work.extension_gpm(behav)
+# Loading work.extension_uart_pkg
+# Loading work.extension_7seg_pkg(body)
+# Loading work.writeback_stage(behav)
+# Loading work.r_w_ram_be(behaviour)
+# Loading work.extension_uart(behav)
+# Loading ieee.std_logic_arith(body)
+# Loading ieee.std_logic_unsigned(body)
+# Loading work.rs232_tx(beh)
+# Loading work.rs232_rx(beh)
+# Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 3 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 4 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 5 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 20 ns Iteration: 1 Instance: /pipeline_tb/writeback_st/data_ram
+run
+run
+do testcore.do
+# ** Warning: (vlib-34) Library already exists at "work".
+# Modifying modelsim.ini
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package mem_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram
+# -- Loading entity r_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r_w_ram_be
+# -- Loading entity r_w_ram_be
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling entity r2_w_ram
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of r2_w_ram
+# -- Loading entity r2_w_ram
+# ** Warning: ../src/r2_w_ram_b.vhd(18): (vcom-1074) Non-locally static OTHERS choice is allowed only if it is the only choice of the only association.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Compiling architecture behaviour of rom
+# -- Loading entity rom
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Compiling package common_pkg
+# -- Compiling package body common_pkg
+# -- Loading package common_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package core_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_uart_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture behav of extension_uart
+# -- Loading entity extension_uart
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling architecture behav of extension_interrupt
+# -- Loading entity extension_interrupt
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package extension_7seg_pkg
+# -- Compiling package body extension_7seg_pkg
+# -- Loading package extension_7seg_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of extension_7seg
+# -- Loading entity extension_7seg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling architecture beh of rs232_tx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_tx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package extension_uart_pkg
+# -- Compiling entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture beh of rs232_rx
+# -- Loading package std_logic_arith
+# -- Loading package std_logic_unsigned
+# -- Loading entity rs232_rx
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav_d of decoder
+# -- Loading entity decoder
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of fetch_stage
+# -- Loading entity fetch_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package mem_pkg
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling architecture behav of decode_stage
+# -- Loading entity decode_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling package alu_pkg
+# -- Compiling package body alu_pkg
+# -- Loading package alu_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture add_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture and_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture or_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture xor_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture shift_op of exec_op
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity alu
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behaviour of alu
+# -- Loading entity alu
+# -- Loading entity exec_op
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling package extension_pkg
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Compiling entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Compiling architecture behav of extension_gpm
+# -- Loading entity extension_gpm
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package alu_pkg
+# -- Compiling architecture behav of execute_stage
+# -- Loading entity execute_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Compiling entity writeback_stage
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Loading package mem_pkg
+# -- Loading package extension_uart_pkg
+# -- Loading package extension_7seg_pkg
+# -- Compiling architecture behav of writeback_stage
+# -- Loading entity writeback_stage
+# ** Warning: ../src/writeback_stage_b.vhd(334): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(350): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(366): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(384): Case choice must be a locally static expression.
+# ** Warning: ../src/writeback_stage_b.vhd(397): Case choice must be a locally static expression.
+# Model Technology ModelSim ALTERA vcom 6.5e Compiler 2010.02 Feb 27 2010
+# -- Loading package standard
+# -- Loading package std_logic_1164
+# -- Loading package numeric_std
+# -- Loading package common_pkg
+# -- Loading package extension_pkg
+# -- Loading package core_pkg
+# -- Compiling entity pipeline_tb
+# -- Compiling architecture behavior of pipeline_tb
+# -- Compiling configuration pipeline_conf_beh
+# -- Loading entity pipeline_tb
+# -- Loading architecture behavior of pipeline_tb
+# -- Loading entity fetch_stage
+# -- Loading entity decode_stage
+# -- Loading package alu_pkg
+# -- Loading entity execute_stage
+# -- Loading entity writeback_stage
+# vsim -t ns work.pipeline_conf_beh
+# Loading std.standard
+# Loading ieee.std_logic_1164(body)
+# Loading ieee.numeric_std(body)
+# Loading work.common_pkg(body)
+# Loading work.extension_pkg
+# Loading work.core_pkg
+# Loading work.alu_pkg(body)
+# Loading work.pipeline_conf_beh
+# Loading work.pipeline_tb(behavior)
+# Loading work.mem_pkg
+# Loading work.fetch_stage(behav)
+# Loading work.r_w_ram(behaviour)
+# Loading work.rom(behaviour)
+# Loading work.decode_stage(behav)
+# Loading work.r2_w_ram(behaviour)
+# Loading work.decoder(behav_d)
+# Loading work.execute_stage(behav)
+# Loading work.alu(behaviour)
+# Loading work.exec_op(add_op)
+# Loading work.exec_op(and_op)
+# Loading work.exec_op(or_op)
+# Loading work.exec_op(xor_op)
+# Loading work.exec_op(shift_op)
+# Loading work.extension_gpm(behav)
+# Loading work.extension_uart_pkg
+# Loading work.extension_7seg_pkg(body)
+# Loading work.writeback_stage(behav)
+# Loading work.r_w_ram_be(behaviour)
+# Loading work.extension_uart(behav)
+# Loading ieee.std_logic_arith(body)
+# Loading ieee.std_logic_unsigned(body)
+# Loading work.rs232_tx(beh)
+# Loading work.rs232_rx(beh)
+# Loading work.extension_7seg(behav)
+# Loading work.extension_interrupt(behav)
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/gpmp_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 0 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/writeback_st
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 1 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 3 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 4 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 0 ns Iteration: 5 Instance: /pipeline_tb/exec_st/alu_inst/shift_inst
+# ** Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0
+# Time: 20 ns Iteration: 1 Instance: /pipeline_tb/writeback_st/data_ram
+run
set_global_assignment -name TOP_LEVEL_ENTITY core_top
set_global_assignment -name VHDL_FILE ../src/core_top.vhd
set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/rom.vhd
+ set_global_assignment -name VHDL_FILE ../src/rom_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/r_w_ram_be.vhd
+ set_global_assignment -name VHDL_FILE ../src/r_w_ram_be_b.vhd
set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd
set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd
+
set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd
set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
- set_global_assignment -name VHDL_FILE ../src/gpm_pkg.vhd
+# set_global_assignment -name VHDL_FILE ../src/gpm_pkg.vhd
set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
set_global_assignment -name VHDL_FILE ../src/extension.vhd
set_global_assignment -name VHDL_FILE ../src/extension_b.vhd
set_location_assignment PIN_L1 -to sys_clk
set_location_assignment PIN_R22 -to sys_res
+ set_location_assignment PIN_G12 -to bus_tx
+ set_location_assignment PIN_F14 -to bus_rx
+
+ set_location_assignment PIN_J2 -to sseg0[0]
+ set_location_assignment PIN_J1 -to sseg0[1]
+ set_location_assignment PIN_H2 -to sseg0[2]
+ set_location_assignment PIN_H1 -to sseg0[3]
+ set_location_assignment PIN_F2 -to sseg0[4]
+ set_location_assignment PIN_F1 -to sseg0[5]
+ set_location_assignment PIN_E2 -to sseg0[6]
+
+ set_location_assignment PIN_E1 -to sseg1[0]
+ set_location_assignment PIN_H6 -to sseg1[1]
+ set_location_assignment PIN_H5 -to sseg1[2]
+ set_location_assignment PIN_H4 -to sseg1[3]
+ set_location_assignment PIN_G3 -to sseg1[4]
+ set_location_assignment PIN_D2 -to sseg1[5]
+ set_location_assignment PIN_D1 -to sseg1[6]
+
+ set_location_assignment PIN_G5 -to sseg2[0]
+ set_location_assignment PIN_G6 -to sseg2[1]
+ set_location_assignment PIN_C2 -to sseg2[2]
+ set_location_assignment PIN_C1 -to sseg2[3]
+ set_location_assignment PIN_E3 -to sseg2[4]
+ set_location_assignment PIN_E4 -to sseg2[5]
+ set_location_assignment PIN_D3 -to sseg2[6]
+
+ set_location_assignment PIN_F4 -to sseg3[0]
+ set_location_assignment PIN_D5 -to sseg3[1]
+ set_location_assignment PIN_D6 -to sseg3[2]
+ set_location_assignment PIN_J4 -to sseg3[3]
+ set_location_assignment PIN_L8 -to sseg3[4]
+ set_location_assignment PIN_F3 -to sseg3[5]
+ set_location_assignment PIN_D4 -to sseg3[6]
+
set_global_assignment -name FMAX_REQUIREMENT "80.00 MHz" -section_id sys_clk
set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
--- /dev/null
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+# Quartus II: Generate Tcl File for Project
+# File: cyc1.tcl
+# Generated on: Thu Dec 23 21:48:06 2010
+
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+ if {[string compare $quartus(project) "dt"]} {
+ puts "Project dt is not open"
+ set make_assignments 0
+ }
+} else {
+ # Only open if not already open
+ if {[project_exists dt]} {
+ project_open -revision dt dt
+ } else {
+ project_new -revision dt dt
+ }
+ set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+ set_global_assignment -name FAMILY Cyclone
+ set_global_assignment -name DEVICE EP1C12Q240C8
+ set_global_assignment -name TOP_LEVEL_ENTITY core_top
+ set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
+ set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:08:54 DECEMBER 16, 2010"
+ set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+ set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+ set_global_assignment -name GENERATE_RBF_FILE ON
+ set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+ set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+ set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+ set_global_assignment -name MISC_FILE /homes/burban/dt/dt.dpf
+ set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+ set_global_assignment -name MISC_FILE /homes/c0726283/calu/dt/dt.dpf
+ set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+ set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+ set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
+ set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
+ set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+ set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+ set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+ set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+ set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
+ set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
+ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+ set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+ set_global_assignment -name VHDL_FILE ../src/r_w_ram_be_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/r_w_ram_be.vhd
+ set_global_assignment -name VHDL_FILE ../src/rom.vhd
+ set_global_assignment -name VHDL_FILE ../src/rom_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd
+ set_global_assignment -name VHDL_FILE ../src/writeback_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/writeback_stage.vhd
+ set_global_assignment -name VHDL_FILE ../src/rw_r_ram_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/rw_r_ram.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd
+ set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
+ set_global_assignment -name VHDL_FILE ../src/r2_w_ram_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd
+ set_global_assignment -name VHDL_FILE ../src/pipeline_tb.vhd
+ set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/fetch_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/fetch_stage.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension.vhd
+ set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
+ set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/decoder.vhd
+ set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
+ set_global_assignment -name VHDL_FILE ../src/core_top.vhd
+ set_global_assignment -name VHDL_FILE ../src/core_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/common_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/alu.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op/xor_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op/shift_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op/or_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op/and_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
+ set_global_assignment -name SMART_RECOMPILE ON
+ set_global_assignment -name ENABLE_CLOCK_LATENCY ON
+ set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
+ set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
+ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+ set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+ set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+ set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
+ set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
+ set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+ set_location_assignment PIN_152 -to sys_clk
+ set_location_assignment PIN_42 -to sys_res
+ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+ # Commit assignments
+ export_assignments
+
+ # Close project
+ if {$need_to_close_project} {
+ project_close
+ }
+}
--- /dev/null
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+# Quartus II: Generate Tcl File for Project
+# File: de1_cyclone_fmax.tcl
+# Generated on: Mon Dec 20 19:47:21 2010
+
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+ if {[string compare $quartus(project) "de1_cyclone"]} {
+ puts "Project de1_cyclone is not open"
+ set make_assignments 0
+ }
+} else {
+ # Only open if not already open
+ if {[project_exists de1_cyclone]} {
+ project_open -revision de1_cyclone de1_cyclone
+ } else {
+ project_new -revision de1_cyclone de1_cyclone
+ }
+ set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+ set_global_assignment -name FAMILY "Cyclone II"
+ set_global_assignment -name DEVICE EP2C20F484C7
+ set_global_assignment -name TOP_LEVEL_ENTITY core_top
+ set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
+ set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:41:06 DECEMBER 20, 2010"
+ set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+ set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (VHDL)"
+ set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
+ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
+ set_global_assignment -name MISC_FILE de1_cyclone.dpf
+ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+ set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+ set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+ set_global_assignment -name VHDL_FILE ../src/core_top.vhd
+ set_global_assignment -name VHDL_FILE ../src/mem_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/r_w_ram.vhd
+ set_global_assignment -name VHDL_FILE ../src/r_w_ram_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/r_w_ram_be.vhd
+ set_global_assignment -name VHDL_FILE ../src/r_w_ram_be_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/rom.vhd
+ set_global_assignment -name VHDL_FILE ../src/rom_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/r2_w_ram.vhd
+ set_global_assignment -name VHDL_FILE ../src/r2_w_ram_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/common_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/core_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/fetch_stage.vhd
+ set_global_assignment -name VHDL_FILE ../src/fetch_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/decoder.vhd
+ set_global_assignment -name VHDL_FILE ../src/decoder_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/decode_stage.vhd
+ set_global_assignment -name VHDL_FILE ../src/decode_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_uart_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_uart.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_uart_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_tx.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_tx_arc.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_rx.vhd
+ set_global_assignment -name VHDL_FILE ../src/rs232_rx_arc.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_7seg_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_7seg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_7seg_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/alu_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op/and_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op/or_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op/xor_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/exec_op/shift_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/alu.vhd
+ set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
+ set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../src/writeback_stage.vhd
+ set_global_assignment -name VHDL_FILE ../src/writeback_stage_b.vhd
+ set_global_assignment -name FMAX_REQUIREMENT "80 MHz" -section_id sys_clk
+ set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+ set_global_assignment -name SMART_RECOMPILE ON
+ set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+ set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+ set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+ set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+ set_global_assignment -name AUTO_PACKED_REGISTERS_STRATIXII NORMAL
+ set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+ set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+ set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+ set_global_assignment -name MUX_RESTRUCTURE OFF
+ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+ set_location_assignment PIN_L1 -to sys_clk
+ set_location_assignment PIN_R22 -to sys_res
+ set_location_assignment PIN_G12 -to bus_tx
+ set_location_assignment PIN_F14 -to bus_rx
+ set_location_assignment PIN_J2 -to sseg0[0]
+ set_location_assignment PIN_J1 -to sseg0[1]
+ set_location_assignment PIN_H2 -to sseg0[2]
+ set_location_assignment PIN_H1 -to sseg0[3]
+ set_location_assignment PIN_F2 -to sseg0[4]
+ set_location_assignment PIN_F1 -to sseg0[5]
+ set_location_assignment PIN_E2 -to sseg0[6]
+ set_location_assignment PIN_E1 -to sseg1[0]
+ set_location_assignment PIN_H6 -to sseg1[1]
+ set_location_assignment PIN_H5 -to sseg1[2]
+ set_location_assignment PIN_H4 -to sseg1[3]
+ set_location_assignment PIN_G3 -to sseg1[4]
+ set_location_assignment PIN_D2 -to sseg1[5]
+ set_location_assignment PIN_D1 -to sseg1[6]
+ set_location_assignment PIN_G5 -to sseg2[0]
+ set_location_assignment PIN_G6 -to sseg2[1]
+ set_location_assignment PIN_C2 -to sseg2[2]
+ set_location_assignment PIN_C1 -to sseg2[3]
+ set_location_assignment PIN_E3 -to sseg2[4]
+ set_location_assignment PIN_E4 -to sseg2[5]
+ set_location_assignment PIN_D3 -to sseg2[6]
+ set_location_assignment PIN_F4 -to sseg3[0]
+ set_location_assignment PIN_D5 -to sseg3[1]
+ set_location_assignment PIN_D6 -to sseg3[2]
+ set_location_assignment PIN_J4 -to sseg3[3]
+ set_location_assignment PIN_L8 -to sseg3[4]
+ set_location_assignment PIN_F3 -to sseg3[5]
+ set_location_assignment PIN_D4 -to sseg3[6]
+ set_instance_assignment -name CLOCK_SETTINGS sys_clk -to sys_clk
+ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+ # Commit assignments
+ export_assignments
+
+ # Close project
+ if {$need_to_close_project} {
+ project_close
+ }
+}
vcom -work work ../src/mem_pkg.vhd
vcom -work work ../src/r_w_ram.vhd
vcom -work work ../src/r_w_ram_b.vhd
+vcom -work work ../src/r_w_ram_be.vhd
+vcom -work work ../src/r_w_ram_be_b.vhd
vcom -work work ../src/r2_w_ram.vhd
vcom -work work ../src/r2_w_ram_b.vhd
+vcom -work work ../src/rom.vhd
+vcom -work work ../src/rom_b.vhd
vcom -work work ../src/common_pkg.vhd
vcom -work work ../src/extension_pkg.vhd
vcom -work work ../src/core_pkg.vhd
+vcom -work work ../src/extension_uart_pkg.vhd
+vcom -work work ../src/extension_uart.vhd
+vcom -work work ../src/extension_uart_b.vhd
+vcom -work work ../src/extension_interrupt.vhd
+vcom -work work ../src/extension_interrupt_b.vhd
+vcom -work work ../src/extension_7seg_pkg.vhd
+vcom -work work ../src/extension_7seg.vhd
+vcom -work work ../src/extension_7seg_b.vhd
+vcom -work work ../src/rs232_tx.vhd
+vcom -work work ../src/rs232_tx_arc.vhd
+vcom -work work ../src/rs232_rx.vhd
+vcom -work work ../src/rs232_rx_arc.vhd
+
vcom -work work ../src/decoder.vhd
vcom -work work ../src/decoder_b.vhd
vcom -work work ../src/fetch_stage.vhd
add wave -radix hexadecimal /pipeline_tb/data_pin
add wave -radix hexadecimal /pipeline_tb/writeback_st/data_ram_read
add wave -radix hexadecimal /pipeline_tb/dmem_wr_en_pin
+add wave -radix hexadecimal /pipeline_tb/writeback_st/dmem_we
+add wave -radix hexadecimal /pipeline_tb/writeback_st/data_addr
+
+add wave -radix hexadecimal /pipeline_tb/tx_pin
+add wave -radix hexadecimal /pipeline_tb/rx_pin
+
add wave -radix decimal /pipeline_tb/cycle_cnt
run 10000 ns
vmap work work
vcom -work work ../src/mem_pkg.vhd
+vcom -work work ../src/rom.vhd
+vcom -work work ../src/rom_b.vhd
vcom -work work ../src/r_w_ram.vhd
vcom -work work ../src/r_w_ram_b.vhd
vcom -work work ../src/r2_w_ram.vhd
vcom -work work ../src/r2_w_ram_b.vhd
vcom -work work ../src/common_pkg.vhd
+vcom -work work ../src/extension_pkg.vhd
vcom -work work ../src/core_pkg.vhd
vcom -work work ../src/decoder.vhd
vcom -work work ../src/decoder_b.vhd
vcom -work work ../src/decode_stage_b.vhd
vcom -work work ../src/alu_pkg.vhd
-vcom -work work ../src/extension_pkg.vhd
vcom -work work ../src/exec_op.vhd
vcom -work work ../src/extension_b.vhd
+vcom -work work ../src/extension_imp_pkg.vhd
+vcom -work work ../src/extension_imp.vhd
+vcom -work work ../src/extension_imp_b.vhd
+
+vcom -work work ../src/extension_7seg_pkg.vhd
+vcom -work work ../src/extension_7seg.vhd
+vcom -work work ../src/extension_7seg_b.vhd
+
vcom -work work ../src/extension_uart_pkg.vhd
vcom -work work ../src/rs232_tx.vhd
vcom -work work ../src/rs232_tx_arc.vhd
+vcom -work work ../src/rs232_rx.vhd
+vcom -work work ../src/rs232_rx_arc.vhd
vcom -work work ../src/extension_uart.vhd
vcom -work work ../src/extension_uart_b.vhd
add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/reg_addr
add wave -group writebackstageregister -radix hexadecimal /pipeline_tb/writeback_st/regfile_val
-
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/ext_uart
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/ext_reg
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w1_st_co_nxt
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w2_uart_config
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w3_uart_send
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/w4_uart_receive
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/data_out
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/new_tx_data
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/bus_tx
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/tx_data
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/tx_rdy
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/tx_rdy_int
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/sys_clk
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/cnt
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/rs232_tx_inst/stop_bit
-add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/uart/bd_rate
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/im_addr
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/im_data
+add wave -group test -radix hexadecimal /pipeline_tb/writeback_st/new_im_data_out
+add wave -group test -radix hexadecimal /pipeline_tb/fetch_st/im_addr
+add wave -group test -radix hexadecimal /pipeline_tb/fetch_st/im_data
+add wave -group test -radix hexadecimal /pipeline_tb/fetch_st/new_im_data_in
run 5000 ns
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
-use work.alu_pkg.all;\r
-\r
-\r
-architecture behaviour of alu is\r
- component exec_op is\r
- port(\r
- --System inputs\r
- \r
- clk : in std_logic;\r
- reset : in std_logic;\r
- --operation inputs\r
- left_operand : in gp_register_t;\r
- right_operand : in gp_register_t;\r
- op_detail : in op_opt_t;\r
- alu_state : in alu_result_rec;\r
- alu_result : out alu_result_rec\r
- ); \r
- end component exec_op;\r
- \r
- signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;\r
- signal left_o, right_o : gp_register_t;\r
- \r
-begin\r
-\r
- add_inst : entity work.exec_op(add_op)\r
- port map(clk,reset,left_o, right_o, op_detail, alu_state, add_result);\r
- \r
- and_inst : entity work.exec_op(and_op)\r
- port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result);\r
-\r
- or_inst : entity work.exec_op(or_op)\r
- port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result);\r
-\r
- xor_inst : entity work.exec_op(xor_op)\r
- port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result);\r
- \r
- shift_inst : entity work.exec_op(shift_op)\r
- port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);\r
-\r
-calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval, pval_nxt)\r
- variable result_v : alu_result_rec;\r
- variable res_prod : std_logic;\r
- variable cond_met : std_logic;\r
- variable mem_en : std_logic;\r
- variable mem_op : std_logic;\r
- variable alu_jump : std_logic;\r
- variable nop : std_logic;\r
- \r
- variable pinc_v, pwr_en_v : std_logic;\r
- \r
- variable prog_cnt_nxt : std_logic_vector(prog_cnt'range);\r
-begin\r
- result_v := alu_state;\r
- \r
- res_prod := '1';\r
- mem_en := '0';\r
- mem_op := '0';\r
- alu_jump := '0';\r
- \r
- left_o <= left_operand;\r
- right_o <= right_operand;\r
-\r
- addr <= add_result.result;\r
- data <= right_operand;\r
- \r
- pinc_v := '0';\r
- pwr_en_v := '0';\r
- \r
- paddr <= (others =>'0');\r
- \r
- result_v.result := add_result.result;\r
- prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);\r
- case cond is\r
- when COND_NZERO =>\r
- cond_met := not(alu_state.status.zero);\r
- when COND_ZERO =>\r
- cond_met := alu_state.status.zero;\r
- when COND_NOFLO =>\r
- cond_met := not(alu_state.status.oflo);\r
- when COND_OFLO =>\r
- cond_met := alu_state.status.oflo;\r
- when COND_NCARRY =>\r
- cond_met := not(alu_state.status.carry);\r
- when COND_CARRY =>\r
- cond_met := alu_state.status.carry;\r
- when COND_NSIGN =>\r
- cond_met := not(alu_state.status.sign);\r
- when COND_SIGN =>\r
- cond_met := alu_state.status.sign;\r
- when COND_ABOVE =>\r
- cond_met := not(alu_state.status.carry) and not(alu_state.status.zero);\r
- when COND_BEQ =>\r
- cond_met := alu_state.status.carry or alu_state.status.zero;\r
- when COND_GEQ =>\r
- cond_met := not(alu_state.status.sign xor alu_state.status.oflo);\r
- when COND_LT =>\r
- cond_met := alu_state.status.sign xor alu_state.status.oflo;\r
- when COND_GT =>\r
- cond_met := not(alu_state.status.zero) and not(alu_state.status.sign xor alu_state.status.oflo);\r
- when COND_LEQ =>\r
- cond_met := alu_state.status.zero or (alu_state.status.sign xor alu_state.status.oflo);\r
- when COND_ALWAYS =>\r
- cond_met := '1';\r
- when COND_NEVER =>\r
- cond_met := '0';\r
- when others => null;\r
- end case;\r
- \r
- nop := (alu_state.alu_jump xnor alu_state.brpr);\r
- cond_met := cond_met and nop;\r
-\r
- case op_group is\r
- when ADDSUB_OP =>\r
- result_v := add_result;\r
- when AND_OP =>\r
- result_v := and_result;\r
- when OR_OP =>\r
- result_v := or_result;\r
- when XOR_OP =>\r
- result_v := xor_result;\r
- when SHIFT_OP =>\r
- result_v := shift_result;\r
- when LDST_OP =>\r
- res_prod := '0';\r
- mem_op := '1';\r
- --right_o <= displacement;\r
- addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));\r
- if op_detail(IMM_OPT) = '1' then\r
- result_v.result := right_operand;\r
- res_prod := '1';\r
- mem_op := '0';\r
- end if;\r
- if op_detail(ST_OPT) = '1' then\r
- mem_en := '1';\r
- end if;\r
- when JMP_OP =>\r
- if op_detail(JMP_REG_OPT) = '0' then\r
- left_o <= prog_cnt;\r
- end if;\r
- alu_jump := '1';\r
- when JMP_ST_OP => \r
- left_o <= prog_cnt;\r
- mem_en := '1';\r
- alu_jump := '1';\r
- mem_op := '1';\r
- pinc_v := '1';\r
- pwr_en_v := '1';\r
- paddr <= (others =>'0');\r
- \r
- addr <= pval;\r
- data <= prog_cnt_nxt;\r
- if op_detail(RET_OPT) = '1' then\r
- addr <= pval_nxt;\r
- mem_en := '0';\r
- pinc_v := '0';\r
- res_prod := '0';\r
- end if;\r
- \r
- end case;\r
- \r
-\r
- result_v.status.zero := '0';\r
- if result_v.result = REG_ZERO then\r
- result_v.status.zero := '1';\r
- end if;\r
- \r
- result_v.status.sign := result_v.result(gp_register_t'high);\r
-\r
- if (op_detail(NO_PSW_OPT) = '1') or (cond_met = '0') then\r
- result_v.status := alu_state.status;\r
- end if;\r
- \r
- result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;\r
- result_v.mem_en := mem_en and cond_met;\r
- result_v.mem_op := mem_op and cond_met;\r
- result_v.alu_jump := alu_jump and cond_met;\r
- result_v.brpr := brpr and nop;\r
- \r
- pwr_en_v := pwr_en_v and cond_met;\r
- \r
- if (result_v.alu_jump = '0') and (brpr = '1') then\r
- result_v.result := (others => '0');\r
- result_v.result(prog_cnt'range) := prog_cnt_nxt;\r
- --result_v.reg_op := '1';\r
- end if;\r
-\r
- alu_result <= result_v;\r
- pinc <= pinc_v;\r
- pwr_en <= pwr_en_v;\r
- \r
-end process calc; \r
-\r
-end architecture behaviour;\r
-\r
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.alu_pkg.all;
+
+
+architecture behaviour of alu is
+ component exec_op is
+ port(
+ --System inputs
+
+ clk : in std_logic;
+ reset : in std_logic;
+ --operation inputs
+ left_operand : in gp_register_t;
+ right_operand : in gp_register_t;
+ op_detail : in op_opt_t;
+ alu_state : in alu_result_rec;
+ alu_result : out alu_result_rec
+ );
+ end component exec_op;
+
+ signal add_result, and_result, or_result, xor_result, shift_result : alu_result_rec;
+ signal left_o, right_o : gp_register_t;
+
+begin
+
+ add_inst : entity work.exec_op(add_op)
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, add_result);
+
+ and_inst : entity work.exec_op(and_op)
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, and_result);
+
+ or_inst : entity work.exec_op(or_op)
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, or_result);
+
+ xor_inst : entity work.exec_op(xor_op)
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, xor_result);
+
+ shift_inst : entity work.exec_op(shift_op)
+ port map(clk,reset,left_o, right_o, op_detail, alu_state, shift_result);
+
+calc: process(left_operand, right_operand,displacement, cond, op_group, op_detail ,alu_state,and_result,add_result,or_result,xor_result,shift_result, prog_cnt,brpr, pval, pval_nxt)
+ variable result_v : alu_result_rec;
+ variable res_prod : std_logic;
+ variable cond_met : std_logic;
+ variable mem_en : std_logic;
+ variable mem_op, hword_op, byte_op : std_logic;
+ variable alu_jump : std_logic;
+ variable nop : std_logic;
+
+ variable pinc_v, pwr_en_v : std_logic;
+
+ variable prog_cnt_nxt : std_logic_vector(prog_cnt'range);
+begin
+ result_v := alu_state;
+
+ res_prod := '1';
+ mem_en := '0';
+ mem_op := '0';
+ hword_op := '0';
+ byte_op := '0';
+ alu_jump := '0';
+
+ left_o <= left_operand;
+ right_o <= right_operand;
+
+ addr <= add_result.result;
+ data <= right_operand;
+
+ pinc_v := '0';
+ pwr_en_v := '0';
+
+ paddr <= (others =>'0');
+
+ result_v.result := add_result.result;
+ if (op_detail(DIRECT_JUMP_OPT) = '0') then
+ prog_cnt_nxt := std_logic_vector(unsigned(prog_cnt)+1);
+ else
+ prog_cnt_nxt := prog_cnt;
+ end if;
+ case cond is
+ when COND_NZERO =>
+ cond_met := not(alu_state.status.zero);
+ when COND_ZERO =>
+ cond_met := alu_state.status.zero;
+ when COND_NOFLO =>
+ cond_met := not(alu_state.status.oflo);
+ when COND_OFLO =>
+ cond_met := alu_state.status.oflo;
+ when COND_NCARRY =>
+ cond_met := not(alu_state.status.carry);
+ when COND_CARRY =>
+ cond_met := alu_state.status.carry;
+ when COND_NSIGN =>
+ cond_met := not(alu_state.status.sign);
+ when COND_SIGN =>
+ cond_met := alu_state.status.sign;
+ when COND_ABOVE =>
+ cond_met := not(alu_state.status.carry) and not(alu_state.status.zero);
+ when COND_BEQ =>
+ cond_met := alu_state.status.carry or alu_state.status.zero;
+ when COND_GEQ =>
+ cond_met := not(alu_state.status.sign xor alu_state.status.oflo);
+ when COND_LT =>
+ cond_met := alu_state.status.sign xor alu_state.status.oflo;
+ when COND_GT =>
+ cond_met := not(alu_state.status.zero) and not(alu_state.status.sign xor alu_state.status.oflo);
+ when COND_LEQ =>
+ cond_met := alu_state.status.zero or (alu_state.status.sign xor alu_state.status.oflo);
+ when COND_ALWAYS =>
+ cond_met := '1';
+ when COND_NEVER =>
+ cond_met := '0';
+ when others => null;
+ end case;
+
+ nop := (alu_state.alu_jump xnor alu_state.brpr);
+ cond_met := cond_met and nop;
+
+ case op_group is
+ when ADDSUB_OP =>
+ result_v := add_result;
+ when AND_OP =>
+ result_v := and_result;
+ when OR_OP =>
+ result_v := or_result;
+ when XOR_OP =>
+ result_v := xor_result;
+ when SHIFT_OP =>
+ result_v := shift_result;
+ when LDST_OP =>
+ res_prod := '0';
+ mem_op := '1';
+ --right_o <= displacement;
+ addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));
+ if op_detail(IMM_OPT) = '1' then
+
+ result_v.result := right_operand;
+
+ if (op_detail(LDI_REPLACE_OPT) = '0') then
+ result_v.result := left_operand;
+ if (op_detail(LOW_HIGH_OPT) = '1') then
+ result_v.result(31 downto 16) := right_operand(31 downto 16);
+ else
+ result_v.result(15 downto 0) := right_operand(15 downto 0);
+ end if;
+ end if;
+
+ res_prod := '1';
+ mem_op := '0';
+ addr(DATA_ADDR_WIDTH + 2) <= '0';
+ end if;
+ if op_detail(ST_OPT) = '1' then
+ mem_en := '1';
+ end if;
+
+ hword_op := op_detail(HWORD_OPT);
+ byte_op := op_detail(BYTE_OPT);
+
+ when JMP_OP =>
+ if op_detail(JMP_REG_OPT) = '0' then
+ left_o <= prog_cnt;
+ end if;
+ alu_jump := '1';
+ when JMP_ST_OP =>
+ left_o <= prog_cnt;
+ mem_en := '1';
+ alu_jump := '1';
+ mem_op := '1';
+ pinc_v := '1';
+ pwr_en_v := '1';
+ paddr <= (others =>'0');
+
+ addr <= pval;
+ data <= prog_cnt_nxt;
+ if op_detail(RET_OPT) = '1' then
+ addr <= pval_nxt;
+ mem_en := '0';
+ pinc_v := '0';
+ res_prod := '0';
+ end if;
+ when STACK_OP =>
+ mem_op := '1';
+ pwr_en_v := '1';
+ if op_detail(PUSH_OPT) = '1' then
+ mem_en := '1';
+ pinc_v := '1';
+ res_prod := '0';
+ addr <= pval_nxt;
+ data <= left_operand;
+ else
+ addr <= std_logic_vector(unsigned(pval_nxt)-4);
+ end if;
+
+ end case;
+
+
+ result_v.status.zero := '0';
+ if result_v.result = REG_ZERO then
+ result_v.status.zero := '1';
+ end if;
+
+ result_v.status.sign := result_v.result(gp_register_t'high);
+
+ if (op_detail(NO_PSW_OPT) = '1') or (cond_met = '0') then
+ result_v.status := alu_state.status;
+ end if;
+
+ result_v.reg_op := not(op_detail(NO_DST_OPT)) and res_prod and cond_met;
+ result_v.mem_en := mem_en and cond_met;
+ result_v.mem_op := mem_op and cond_met;
+ result_v.alu_jump := alu_jump and cond_met;
+ result_v.brpr := brpr and nop;
+
+ result_v.hw_op := hword_op and cond_met;
+ result_v.byte_op := byte_op and cond_met;
+
+ pwr_en_v := pwr_en_v and cond_met;
+
+ if (result_v.alu_jump = '0') and (brpr = '1') then
+ result_v.result := (others => '0');
+ result_v.result(prog_cnt'range) := prog_cnt_nxt;
+ --result_v.reg_op := '1';
+ end if;
+
+ -- if result_v.mem_op = '0' then --- do this if selecting enable for extension modules is too slow.
+ -- addr <= (others => '0');
+ -- end if;
+ alu_result <= result_v;
+ pinc <= pinc_v;
+ pwr_en <= pwr_en_v;
+
+end process calc;
+
+end architecture behaviour;
+
subtype word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
subtype gp_register_t is word_t;
-
+
+ subtype byte_en_t is std_logic_vector((gp_register_t'length/byte_t'length-1) downto 0);
constant REG_ZERO : gp_register_t := (others => '0');
constant INSTR_ADDR_WIDTH : INTEGER := 32;
constant PHYS_INSTR_ADDR_WIDTH : INTEGER := 11;
+ constant ROM_INSTR_ADDR_WIDTH : INTEGER := 7;
constant REG_ADDR_WIDTH : INTEGER := 4;
constant DATA_ADDR_WIDTH : INTEGER := 11;
constant PHYS_DATA_ADDR_WIDTH : INTEGER := 32;
constant COND_WIDTH : INTEGER := 4;
constant DATA_END_ADDR : integer := ((2**DATA_ADDR_WIDTH)-1);
+ constant ROM_USE : std_logic := '1';
+ constant RAM_USE : std_logic := '0';
subtype instruction_word_t is std_logic_vector(WORD_WIDTH-1 downto 0);
subtype instruction_addr_t is std_logic_vector(INSTR_ADDR_WIDTH-1 downto 0);
constant SUB_OPT : integer := 1;
constant ARITH_OPT : integer := 1;
+ constant HWORD_OPT : integer := 1;
+ constant PUSH_OPT : integer := 1;
+ constant LOW_HIGH_OPT : integer := 1;
+ constant DIRECT_JUMP_OPT : integer := 1;
constant CARRY_OPT : integer := 2;
+ constant BYTE_OPT : integer := 2;
+ constant LDI_REPLACE_OPT : integer := 2;
constant RIGHT_OPT : integer := 3;
constant JMP_REG_OPT : integer := 3;
constant NO_PSW_OPT : integer := 4;--no sharing
constant NO_DST_OPT : integer := 5; --no sharing
- type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP, LDST_OP, JMP_OP, JMP_ST_OP);
+ type op_info_t is (ADDSUB_OP,AND_OP,OR_OP, XOR_OP,SHIFT_OP, LDST_OP, JMP_OP, JMP_ST_OP, STACK_OP);
subtype op_opt_t is std_logic_vector(NUM_OP_OPT_WIDTH-1 downto 0);
+
+ type interrupt_t is (IDLE, UART);
-
+ constant UART_INT_EN_BIT : integer := 1;
+ constant GLOBAL_INT_EN_BIT : integer := 0;
+
+ constant UART_INT_VECTOR : std_logic_vector(PHYS_INSTR_ADDR_WIDTH-1 downto 0) := "00000000001"; --integer := 1;
+
type instruction_rec is record
predicates : std_logic_vector(3 downto 0);
jmptype : std_logic_vector(1 downto 0);
- high_low, fill, signext, bp: std_logic;
+ high_low, fill, signext, bp, int: std_logic;
op_detail : op_opt_t;
op_group : op_info_t;
end record;
+
type read_through_write_rec is record
rtw_reg : gp_register_t;
dmem_write_en : std_logic; --ureg
hword : std_logic; --ureg
byte_s : std_logic;
+ byte_en : byte_en_t;
+ data : gp_register_t;
end record;
+ type exec2wb_rec is record
+ result : gp_register_t; --reg (alu result or jumpaddr)
+ result_addr : gp_addr_t; --reg
+ address : word_t; --ureg
+ ram_data : word_t; --ureg
+ alu_jmp : std_logic; --reg
+ br_pred : std_logic; --reg
+ write_en : std_logic; --reg (register file) bei jump 1 wenn addr in result
+ dmem_en : std_logic; --ureg (jump addr in mem or in address)
+ dmem_write_en : std_logic; --ureg
+ hword : std_logic; --ureg
+ byte_s : std_logic; --ureg
+ end record;
function inc(value : in std_logic_vector; constant by : in integer := 1) return std_logic_vector;
function log2c(constant value : in integer range 0 to integer'high) return integer;
prediction_result : in instruction_addr_t;
branch_prediction_bit : in std_logic;
alu_jump_bit : in std_logic;
+ int_req : in interrupt_t;
+ new_im_data_in : in std_logic;
+ im_addr : in gp_register_t;
+ im_data : in gp_register_t;
--Data outputs
instruction : out instruction_word_t;
-- active reset value
RESET_VALUE : std_logic;
-- active logic value
- LOGIC_ACT : std_logic
-
+ LOGIC_ACT : std_logic;
+ FPGATYPE : string
);
port(
--System inputs
reg_we : out std_logic;
reg_addr : out gp_addr_t;
jump_addr : out instruction_addr_t;
- jump : out std_logic
+ jump : out std_logic;
+ -- same here
+ bus_tx : out std_logic;
+ bus_rx : in std_logic;
+ new_im_data_out : out std_logic;
+ im_addr : out gp_register_t;
+ im_data : out gp_register_t;
+
+ sseg0 : out std_logic_vector(0 to 6);
+ sseg1 : out std_logic_vector(0 to 6);
+ sseg2 : out std_logic_vector(0 to 6);
+ sseg3 : out std_logic_vector(0 to 6);
+
+ int_req : out interrupt_t
+
);
end component writeback_stage;
port(
--System input pins
+ sys_res : in std_logic;
sys_clk : in std_logic;
- sys_res : in std_logic;
-- result : out gp_register_t;
- jump_result : out instruction_addr_t
-- reg_wr_data : out gp_register_t
+ -- uart
+ bus_tx : out std_logic;
+ bus_rx : in std_logic;
+ sseg0 : out std_logic_vector(0 to 6);
+ sseg1 : out std_logic_vector(0 to 6);
+ sseg2 : out std_logic_vector(0 to 6);
+ sseg3 : out std_logic_vector(0 to 6)
);
end core_top;
architecture behav of core_top is
+ constant SYNC_STAGES : integer := 2;
+ constant RESET_VALUE : std_logic := '0';
+
+ signal jump_result : instruction_addr_t;
signal jump_result_pin : instruction_addr_t;
signal prediction_result_pin : instruction_addr_t;
signal branch_prediction_bit_pin : std_logic;
signal gpm_in_pin : extmod_rec;
signal gpm_out_pin : gp_register_t;
signal nop_pin : std_logic;
+
+ signal sync : std_logic_vector(1 to SYNC_STAGES);
+ signal sys_res_n : std_logic;
+ signal int_req : interrupt_t;
+ signal new_im_data : std_logic;
+ signal im_addr, im_data : gp_register_t;
+
+ signal vers, vers_nxt : exec2wb_rec;
begin
fetch_st : fetch_stage
port map (
--System inputs
clk => sys_clk, --: in std_logic;
- reset => sys_res, --: in std_logic;
+ reset => sys_res_n, --: in std_logic;
--Data inputs
jump_result => jump_result_pin, --: in instruction_addr_t;
prediction_result => prediction_result_pin, --: in instruction_addr_t;
branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
-
+ int_req => int_req,
+ -- instruction memory program port :D
+ new_im_data_in => new_im_data,
+ im_addr => im_addr,
+ im_data => im_data,
--Data outputs
instruction => instruction_pin, --: out instruction_word_t
prog_cnt => prog_cnt_pin
port map (
--System inputs
clk => sys_clk, --: in std_logic;
- reset => sys_res, -- : in std_logic;
+ reset => sys_res_n, -- : in std_logic;
--Data inputs
instruction => instruction_pin, --: in instruction_word_t;
exec_st : execute_stage
generic map('0')
- port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+ port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
- writeback_st : writeback_stage
- generic map('0', '1')
- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+ vers_nxt.result <= result_pin;
+ vers_nxt.result_addr <= result_addr_pin;
+ vers_nxt.address <= addr_pin;
+ vers_nxt.ram_data <= data_pin;
+ vers_nxt.alu_jmp <= alu_jump_pin;
+ vers_nxt.br_pred <= brpr_pin;
+ vers_nxt.write_en <= wr_en_pin;
+ vers_nxt.dmem_en <= dmem_pin;
+ vers_nxt.dmem_write_en <= dmem_wr_en_pin;
+ vers_nxt.hword <= hword_pin;
+ vers_nxt.byte_s <= byte_s_pin;
+
+-- writeback_st : writeback_stage
+-- generic map('0', '1')
+-- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
+-- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+-- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+--
+
+ writeback_st : writeback_stage
+ generic map('0', '1', "altera")
+ port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
+ vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
+ -- instruction memory program port :D
+ new_im_data, im_addr, im_data,
+ sseg0, sseg1, sseg2, sseg3, int_req);
+
+
+syn: process(sys_clk, sys_res)
+begin
+ if sys_res = '0' then
+-- vers.result <= (others => '0');
+-- vers.result_addr <= (others => '0');
+-- vers.address <= (others => '0');
+-- vers.ram_data <= (others => '0');
+-- vers.alu_jmp <= '0';
+-- vers.br_pred <= '0';
+-- vers.write_en <= '0';
+-- vers.dmem_en <= '0';
+-- vers.dmem_write_en <= '0';
+-- vers.hword <= '0';
+-- vers.byte_s <= '0';
+
+ sync <= (others => '0');
+
+ elsif rising_edge(sys_clk) then
+-- vers <= vers_nxt;
+ sync(1) <= sys_res;
+ for i in 2 to SYNC_STAGES loop
+ sync(i) <= sync(i - 1);
+ end loop;
+
+ end if;
+
+end process;
-
+sys_res_n <= sync(SYNC_STAGES);
+
--init : process(all)
--begin
nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
jump_result <= prog_cnt_pin; --jump_result_pin;
+-- sys_res <= '1';
-- reg_wr_data <= reg_wr_data_pin;
+
end behav;
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+use work.extension_pkg.all;
+
+entity core_top is
+
+ port(
+ --System input pins
+ sys_res : in std_logic;
+ sys_clk : in std_logic;
+-- result : out gp_register_t;
+-- reg_wr_data : out gp_register_t
+ -- uart
+ bus_tx : out std_logic;
+ bus_rx : in std_logic;
+
+ sseg0 : out std_logic_vector(0 to 6);
+ sseg1 : out std_logic_vector(0 to 6);
+ sseg2 : out std_logic_vector(0 to 6);
+ sseg3 : out std_logic_vector(0 to 6)
+ );
+
+end core_top;
+
+architecture behav of core_top is
+
+ constant SYNC_STAGES : integer := 2;
+ constant RESET_VALUE : std_logic := '0';
+
+ signal jump_result : instruction_addr_t;
+ signal jump_result_pin : instruction_addr_t;
+ signal prediction_result_pin : instruction_addr_t;
+ signal branch_prediction_bit_pin : std_logic;
+ signal alu_jump_bit_pin : std_logic;
+ signal instruction_pin : instruction_word_t;
+ signal prog_cnt_pin : instruction_addr_t;
+
+ signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+ signal reg_wr_data_pin : gp_register_t;
+ signal reg_we_pin : std_logic;
+ signal to_next_stage : dec_op;
+
+-- signal reg1_rd_data_pin : gp_register_t;
+-- signal reg2_rd_data_pin : gp_register_t;
+
+ signal result_pin : gp_register_t;--reg
+ signal result_addr_pin : gp_addr_t;--reg
+ signal addr_pin : word_t; --memaddr
+ signal data_pin : gp_register_t; --mem data --ureg
+ signal alu_jump_pin : std_logic;--reg
+ signal brpr_pin : std_logic; --reg
+ signal wr_en_pin : std_logic;--regop --reg
+ signal dmem_pin : std_logic;--memop
+ signal dmem_wr_en_pin : std_logic;
+ signal hword_pin : std_logic;
+ signal byte_s_pin : std_logic;
+
+ signal gpm_in_pin : extmod_rec;
+ signal gpm_out_pin : gp_register_t;
+ signal nop_pin : std_logic;
+
+ signal sync : std_logic_vector(1 to SYNC_STAGES);
+ signal sys_res_n : std_logic;
+
+ signal int_req : interrupt_t;
+
+ signal new_im_data : std_logic;
+ signal im_addr, im_data : gp_register_t;
+
+ signal vers, vers_nxt : exec2wb_rec;
+begin
+
+ fetch_st : fetch_stage
+ generic map (
+
+ '0',
+ '1'
+ )
+
+ port map (
+ --System inputs
+ clk => sys_clk, --: in std_logic;
+ reset => sys_res_n, --: in std_logic;
+
+ --Data inputs
+ jump_result => jump_result_pin, --: in instruction_addr_t;
+ prediction_result => prediction_result_pin, --: in instruction_addr_t;
+ branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
+ alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+ int_req => int_req,
+ -- instruction memory program port :D
+ new_im_data_in => new_im_data,
+ im_addr => im_addr,
+ im_data => im_data,
+ --Data outputs
+ instruction => instruction_pin, --: out instruction_word_t
+ prog_cnt => prog_cnt_pin
+ );
+
+ decode_st : decode_stage
+ generic map (
+ -- active reset value
+ '0',
+ -- active logic value
+ '1'
+
+ )
+ port map (
+ --System inputs
+ clk => sys_clk, --: in std_logic;
+ reset => sys_res_n, -- : in std_logic;
+
+ --Data inputs
+ instruction => instruction_pin, --: in instruction_word_t;
+ prog_cnt => prog_cnt_pin,
+ reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
+ reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
+ reg_we => reg_we_pin, --: in std_logic;
+ nop => nop_pin,
+
+ --Data outputs
+ branch_prediction_res => prediction_result_pin, --: instruction_word_t;
+ branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
+ to_next_stage => to_next_stage
+ );
+
+ exec_st : execute_stage
+ generic map('0')
+ port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+ data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
+
+
+ vers_nxt.result <= result_pin;
+ vers_nxt.result_addr <= result_addr_pin;
+ vers_nxt.address <= addr_pin;
+ vers_nxt.ram_data <= data_pin;
+ vers_nxt.alu_jmp <= alu_jump_pin;
+ vers_nxt.br_pred <= brpr_pin;
+ vers_nxt.write_en <= wr_en_pin;
+ vers_nxt.dmem_en <= dmem_pin;
+ vers_nxt.dmem_write_en <= dmem_wr_en_pin;
+ vers_nxt.hword <= hword_pin;
+ vers_nxt.byte_s <= byte_s_pin;
+
+-- writeback_st : writeback_stage
+-- generic map('0', '1')
+-- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
+-- wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+-- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+--
+
+ writeback_st : writeback_stage
+ generic map('0', '1', "s3e")
+ port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
+ vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
+ -- instruction memory program port :D
+ new_im_data, im_addr, im_data,
+ sseg0, sseg1, sseg2, sseg3, int_req);
+
+
+syn: process(sys_clk, sys_res)
+
+begin
+
+ if sys_res = '0' then
+-- vers.result <= (others => '0');
+-- vers.result_addr <= (others => '0');
+-- vers.address <= (others => '0');
+-- vers.ram_data <= (others => '0');
+-- vers.alu_jmp <= '0';
+-- vers.br_pred <= '0';
+-- vers.write_en <= '0';
+-- vers.dmem_en <= '0';
+-- vers.dmem_write_en <= '0';
+-- vers.hword <= '0';
+-- vers.byte_s <= '0';
+
+ sync <= (others => '0');
+
+ elsif rising_edge(sys_clk) then
+-- vers <= vers_nxt;
+ sync(1) <= sys_res;
+ for i in 2 to SYNC_STAGES loop
+ sync(i) <= sync(i - 1);
+ end loop;
+
+ end if;
+
+end process;
+
+sys_res_n <= sync(SYNC_STAGES);
+
+--init : process(all)
+
+--begin
+-- jump_result_pin <= (others => '0');
+-- alu_jump_bit_pin <= '0';
+-- reg_w_addr_pin <= (others => '0');
+-- reg_wr_data_pin <= (others => '0');
+-- reg_we_pin <= '0';
+
+--end process;
+
+-- result <= result_pin;
+ nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
+
+ jump_result <= prog_cnt_pin; --jump_result_pin;
+-- sys_res <= '1';
+
+-- reg_wr_data <= reg_wr_data_pin;
+
+end behav;
-- async process: calculates branch prediction
-br_pred: process(instr_spl, prog_cnt)
+br_pred: process(instr_spl, prog_cnt, reset)
begin
branch_prediction_bit <= '0';
if ((instr_spl.opcode = "10110" or instr_spl.opcode = "10111") and instr_spl.bp = '1') then
- branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt)); --both 32 bit
+ if instr_spl.int = '0' then
+ branch_prediction_res <= std_logic_vector(unsigned(instr_spl.immediate) + unsigned(prog_cnt)); --both 32 bit
+ else
+ branch_prediction_res <= instr_spl.immediate;
+ end if;
branch_prediction_bit <= '1';
end if;
+ if reset = RESET_VALUE then
+ branch_prediction_bit <= '0';
+ end if;
+
end process;
end behav;
instr_s.bp := '0';
instr_s.op_detail := (others => '0');
instr_s.displacement := (others => '0');
+ instr_s.int := '0';
instr_s.op_group := ADDSUB_OP;
instr_s.op_detail(IMM_OPT) := '1';
instr_s.op_detail(NO_PSW_OPT) := instruction(0);
- if (instr_s.opcode = "00111") then
+ if (instr_s.opcode = "00101") then
instr_s.op_group := AND_OP;
end if;
-- instr_s.sreg_update := instruction(0);
--
--=================================================================
- if (instr_s.opcode = "01010" or instr_s.opcode = "01011") then
+ if (instr_s.opcode = "01010") then
-- when "01010" => --shift
instr_s.reg_dest_addr := instruction(22 downto 19);
end if;
if (instr_s.opcode = "11010") then --ldi
+ instr_s.reg_src1_addr := instr_s.reg_dest_addr;
+ instr_s.op_detail(LOW_HIGH_OPT) := instr_s.high_low;
+ instr_s.op_detail(LDI_REPLACE_OPT) := instr_s.signext;
+
if (instr_s.high_low = '1') then
instr_s.immediate(31 downto 16) := instruction(18 downto 3);
instr_s.immediate(15 downto 0) := (others => '0');
else
instr_s.immediate(15 downto 0) := instruction(18 downto 3);
instr_s.immediate(31 downto 16) := (others => '0');
-
- --instr_s.immediate(11 downto 0) := instruction(14 downto 3);
- --instr_s.immediate(WORD_WIDTH-1 downto 12) := (others => '0');
end if;
if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
instr_s.op_detail(IMM_OPT) := '1';
end if;
+
+ if (instr_s.opcode = "10000") then
+ instr_s.op_detail(HWORD_OPT) := '1';
+ end if;
+
+ if (instr_s.opcode = "10010") then
+ instr_s.op_detail(BYTE_OPT) := '1';
+ end if;
end if;
-- when "10000" => --ldh
instr_s.reg_src1_addr := instruction(18 downto 15); -- mem addr
instr_s.displacement(14 downto 0) := instruction(14 downto 0);
instr_s.op_detail(NO_PSW_OPT) := '1';
- instr_s.op_detail(ST_OPT) := '1';
+ instr_s.op_detail(ST_OPT) := '1';
instr_s.op_group := LDST_OP;
if (instr_s.displacement(14) = '1') then
instr_s.displacement(31 downto 15) := (others => '1');
end if;
+
+ if (instr_s.opcode = "10001") then
+ instr_s.op_detail(HWORD_OPT) := '1';
+ end if;
+
+ if (instr_s.opcode = "10011") then
+ instr_s.op_detail(BYTE_OPT) := '1';
+ end if;
+
end if;
+ -- ===============================================================
+
+ if (instr_s.opcode = "01011") then -- stack op
+ instr_s.reg_src1_addr := instruction(22 downto 19);
+ instr_s.reg_dest_addr := instruction(22 downto 19);
+ instr_s.op_group := STACK_OP;
+ instr_s.op_detail(NO_PSW_OPT) := '1';
+
+ case instruction(18 downto 17) is
+ when "00" =>
+ instr_s.op_detail(PUSH_OPT) := '0';
+
+ when "01" => null;
+
+ when "10" => null;
+
+ when "11" =>
+ instr_s.op_detail(PUSH_OPT) := '1';
+
+ when others => null;
+ end case;
+
+ end if;
+
-- when "10001" => --sth
-- instr_s.reg_src1_addr := instruction(22 downto 19);
-- instr_s.reg_src2_addr := instruction(18 downto 15);
instr_s.jmptype := instruction(3 downto 2);
instr_s.signext := instruction(0);
instr_s.op_detail(NO_PSW_OPT) := '1';
-
+ instr_s.op_detail(DIRECT_JUMP_OPT) := instruction(4);
+ instr_s.int := instruction(4);
if (instr_s.opcode = "10110") then
instr_s.op_detail(IMM_OPT) := '1';
variable addcarry : unsigned(carry_res'range);
begin
alu_result_v := alu_state;
-
- addcarry := (others =>'0');
- addcarry(0) := alu_state.status.carry and addc;
-
- complement := inc(not(right_operand));
- l_neg := left_operand(gp_register_t'high);
-
- carry_res := unsigned('0' & left_operand)+addcarry;
- oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high));
-
+ addcarry := (others => '0');
+ addcarry(0):= (alu_state.status.carry and addc) or (sub and not(addc));
if sub = '1' then
- tmp_right_operand := unsigned('0' & complement);
+ carry_res := unsigned('0' & left_operand)+unsigned('0' & not(right_operand))+addcarry;
else
- tmp_right_operand := unsigned('0' & right_operand);
+ carry_res := unsigned('0' & left_operand)+unsigned('0' & right_operand)+addcarry;
end if;
+ alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
+ alu_result_v.status.carry := carry_res(carry_res'high);
+ alu_result_v.status.oflo := add_oflo(left_operand(gp_register_t'high),right_operand(gp_register_t'high) xor sub, carry_res(gp_register_t'high));
+ -- addcarry := (others =>'0');
+ -- addcarry(0) := alu_state.status.carry and addc;
- l_neg := carry_res(gp_register_t'high);
- r_neg := tmp_right_operand(gp_register_t'high);
+ -- complement := inc(not(right_operand));
+ -- l_neg := left_operand(gp_register_t'high);
- carry_res := carry_res + tmp_right_operand;
- oflo2 := add_oflo(l_neg,r_neg,carry_res(gp_register_t'high));
+ -- carry_res := unsigned('0' & left_operand)+addcarry;
+ -- oflo1 := add_oflo(l_neg,'0',carry_res(gp_register_t'high));
+
+ -- if sub = '1' then
+ -- tmp_right_operand := unsigned('0' & complement);
+ -- else
+ -- tmp_right_operand := unsigned('0' & right_operand);
+ -- end if;
+
+ -- l_neg := carry_res(gp_register_t'high);
+ -- r_neg := tmp_right_operand(gp_register_t'high);
+
+ -- carry_res := carry_res + tmp_right_operand;
+ -- oflo2 := add_oflo(l_neg,r_neg,carry_res(gp_register_t'high));
- alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
- alu_result_v.status.carry := carry_res(carry_res'high);
- -- alu_result_v.result := (0 => '1', others => '0');
+ -- alu_result_v.result := std_logic_vector(carry_res(gp_register_t'range));
+ -- alu_result_v.status.carry := carry_res(carry_res'high);
+ -- -- alu_result_v.result := (0 => '1', others => '0');
- alu_result_v.status.oflo := oflo1 or oflo2;
+ -- alu_result_v.status.oflo := oflo1 or oflo2;
- --sign will be set globally.
- --zero will be set globally.
+ -- --sign will be set globally.
+ -- --zero will be set globally.
alu_result <= alu_result_v;
end process;
alu_jump <= reg.alu_jump;
brpr <= reg.brpr;
wr_en <= reg.wr_en;
+
dmem <= alu_nxt.mem_op;
+
--dmem <= reg.result(4);
+
dmem_write_en <= alu_nxt.mem_en;
+
--dmem_write_en <= reg.result(0);
--dmem_write_en <= '1';
+
hword <= alu_nxt.hw_op;
+
--hword <= reg.result(1);
+
byte_s <= alu_nxt.byte_op;
--addr <= alu_nxt.result;
--- /dev/null
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.numeric_std.all;\r
+\r
+use work.common_pkg.all;\r
+use work.extension_pkg.all;\r
+use work.extension_7seg_pkg.all;\r
+\r
+entity extension_7seg is\r
+\r
+ generic(\r
+ RESET_VALUE : std_logic\r
+ );\r
+ port(\r
+ --System inputs\r
+ sys_clk : in std_logic;\r
+ sys_res_n : in std_logic;\r
+ -- general extension interface \r
+ ext_reg : in extmod_rec;\r
+-- data_out : out gp_register_t;\r
+ --Control input\r
+-- val : in std_logic_vector(4 downto 0);\r
+-- pos : in std_logic_vector(1 downto 0);\r
+-- act : std_logic;\r
+ --Output\r
+ o_digit0 : out std_logic_vector(0 to 6);\r
+ o_digit1 : out std_logic_vector(0 to 6);\r
+ o_digit2 : out std_logic_vector(0 to 6);\r
+ o_digit3 : out std_logic_vector(0 to 6)\r
+ );\r
+ \r
+end extension_7seg;\r
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+--use work.math_pkg.all;
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+use work.mem_pkg.all;
+use work.extension_pkg.all;
+use work.extension_7seg_pkg.all;
+
+architecture behav of extension_7seg is
+
+signal s_state, s_state_nxt : sseg_state_rec;
+signal ext_reg_r : extmod_rec;
+
+begin
+
+seg_syn: process(sys_clk, sys_res_n)
+
+begin
+
+ if (sys_res_n = RESET_VALUE) then
+
+ s_state.digit0 <= (others => '0');--set(0,7);
+ s_state.digit1 <= (others => '0');--set(0,7);
+ s_state.digit2 <= (others => '0');--set(0,7);
+ s_state.digit3 <= (others => '0');--set(0,7);
+
+ ext_reg_r.sel <='0';
+ ext_reg_r.wr_en <= '0';
+ ext_reg_r.byte_en <= (others => '0');
+ ext_reg_r.data <= (others => '0');
+ ext_reg_r.addr <= (others => '0');
+
+ elsif rising_edge(sys_clk) then
+
+ s_state <= s_state_nxt;
+ ext_reg_r <= ext_reg;
+
+ end if;
+
+end process;
+
+seg_asyn: process(s_state, ext_reg_r)
+
+begin
+ s_state_nxt <= s_state;
+
+ if ext_reg_r.sel = '1' and ext_reg_r.wr_en = '1' then
+
+
+-- case ext_reg_r.byte_en(1 downto 0) is
+-- when "00" => null;
+-- s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
+-- s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
+-- s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
+-- s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
+-- when others =>
+-- s_state_nxt.digit0 <= (others => '1');
+-- s_state_nxt.digit1 <= (others => '1');
+-- s_state_nxt.digit2 <= (others => '1');
+-- s_state_nxt.digit3 <= (others => '1');
+-- end case;
+
+ if (ext_reg_r.byte_en(0) = '1') then
+ s_state_nxt.digit0 <= digit_decode('0' & ext_reg_r.data(3 downto 0));
+ s_state_nxt.digit1 <= digit_decode('0' & ext_reg_r.data(7 downto 4));
+ end if;
+ if (ext_reg_r.byte_en(1) = '1') then
+ s_state_nxt.digit2 <= digit_decode('0' & ext_reg_r.data(11 downto 8));
+ s_state_nxt.digit3 <= digit_decode('0' & ext_reg_r.data(15 downto 12));
+ end if;
+
+ end if;
+
+end process; --ps2_next
+
+seg_out: process(s_state)
+begin
+
+ o_digit0 <= not(s_state.digit0);
+ o_digit1 <= not(s_state.digit1);
+ o_digit2 <= not(s_state.digit2);
+ o_digit3 <= not(s_state.digit3);
+
+end process;
+
+end behav;
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+
+package extension_7seg_pkg is
+
+ constant SEGMENT_G : std_logic_vector(0 to 6) := "0000001";
+ constant SEGMENT_F : std_logic_vector(0 to 6) := "0000010";
+ constant SEGMENT_E : std_logic_vector(0 to 6) := "0000100";
+ constant SEGMENT_D : std_logic_vector(0 to 6) := "0001000";
+ constant SEGMENT_C : std_logic_vector(0 to 6) := "0010000";
+ constant SEGMENT_B : std_logic_vector(0 to 6) := "0100000";
+ constant SEGMENT_A : std_logic_vector(0 to 6) := "1000000";
+
+ constant DIGIT_0 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_E or SEGMENT_F;
+ constant DIGIT_1 : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_C;
+ constant DIGIT_2 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_G or SEGMENT_E or SEGMENT_D;
+ constant DIGIT_3 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_G;
+ constant DIGIT_4 : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_C or SEGMENT_G or SEGMENT_F;
+ constant DIGIT_5 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_G or SEGMENT_C or SEGMENT_D;
+ constant DIGIT_6 : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_D or SEGMENT_C or SEGMENT_G;
+ constant DIGIT_7 : std_logic_vector(0 to 6) := SEGMENT_A or DIGIT_1;
+ constant DIGIT_8 : std_logic_vector(0 to 6) := SEGMENT_G or DIGIT_0;
+ constant DIGIT_9 : std_logic_vector(0 to 6) := SEGMENT_B or DIGIT_5;
+ constant DIGIT_A : std_logic_vector(0 to 6) := DIGIT_1 or SEGMENT_A or SEGMENT_G or SEGMENT_E or SEGMENT_F;
+ constant DIGIT_B : std_logic_vector(0 to 6) := SEGMENT_F or SEGMENT_E or SEGMENT_D or SEGMENT_C or SEGMENT_G;
+ constant DIGIT_C : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_D;
+ constant DIGIT_D : std_logic_vector(0 to 6) := SEGMENT_B or SEGMENT_G or SEGMENT_E or SEGMENT_D or SEGMENT_C;
+ constant DIGIT_E : std_logic_vector(0 to 6) := DIGIT_C or SEGMENT_G;
+ constant DIGIT_F : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_F or SEGMENT_E or SEGMENT_G;
+ constant DIGIT_MINUS : std_logic_vector(0 to 6) := SEGMENT_G;
+ constant DIGIT_CLEAR : std_logic_vector(0 to 6) := SEGMENT_A or SEGMENT_B or SEGMENT_C or SEGMENT_D or SEGMENT_E or SEGMENT_F or SEGMENT_G;
+
+ subtype sseg_digit is std_logic_vector(4 downto 0);
+
+ type sseg_state_rec is record
+ digit0 : std_logic_vector(0 to 6);
+ digit1 : std_logic_vector(0 to 6);
+ digit2 : std_logic_vector(0 to 6);
+ digit3 : std_logic_vector(0 to 6);
+ end record;
+
+ function digit_decode(value : sseg_digit) return std_logic_vector;
+
+ component extension_7seg
+
+ generic(
+ RESET_VALUE : std_logic
+ );
+ port(
+ --System inputs
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+ -- general extension interface
+ ext_reg : in extmod_rec;
+-- data_out : out gp_register_t;
+ --Control input
+-- val : in std_logic_vector(4 downto 0);
+-- pos : in std_logic_vector(1 downto 0);
+-- act : std_logic;
+ --Output
+ o_digit0 : out std_logic_vector(0 to 6);
+ o_digit1 : out std_logic_vector(0 to 6);
+ o_digit2 : out std_logic_vector(0 to 6);
+ o_digit3 : out std_logic_vector(0 to 6)
+ );
+ end component extension_7seg;
+
+end extension_7seg_pkg;
+
+package body extension_7seg_pkg is
+
+ function digit_decode(value : sseg_digit) return std_logic_vector is
+
+ begin
+ case value is
+ when "00000" => return DIGIT_0;
+ when "00001" => return DIGIT_1;
+ when "00010" => return DIGIT_2;
+ when "00011" => return DIGIT_3;
+ when "00100" => return DIGIT_4;
+ when "00101" => return DIGIT_5;
+ when "00110" => return DIGIT_6;
+ when "00111" => return DIGIT_7;
+ when "01000" => return DIGIT_8;
+ when "01001" => return DIGIT_9;
+ when "01010" => return DIGIT_A;
+ when "01011" => return DIGIT_B;
+ when "01100" => return DIGIT_C;
+ when "01101" => return DIGIT_D;
+ when "01110" => return DIGIT_E;
+ when "01111" => return DIGIT_F;
+ when "10000" => return "1111111";
+ --when "11111" => return DIGIT_MINUS;
+ when OTHERS => return DIGIT_CLEAR;
+ end case;
+
+ end function digit_decode;
+
+end extension_7seg_pkg;
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+use work.extension_imp_pkg.all;
+
+
+entity extension_imp is
+
+ generic (
+ -- active reset value
+ RESET_VALUE : std_logic
+ );
+ port(
+ --System inputs
+ clk : in std_logic;
+ reset : in std_logic;
+ -- general extension interface
+ ext_reg : in extmod_rec;
+ data_out : out gp_register_t;
+ -- Input
+
+ -- Ouput
+ im_addr : out gp_register_t;
+ im_data : out gp_register_t;
+ new_im_data_out : out std_logic
+ );
+
+end extension_imp;
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.STD_LOGIC_ARITH.ALL;
+use IEEE.STD_LOGIC_UNSIGNED.ALL;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+
+use work.mem_pkg.all;
+use work.extension_pkg.all;
+use work.extension_imp_pkg.all;
+
+architecture behav of extension_imp is
+
+signal w1_st_co, w1_st_co_nxt, w2_im_addr, w2_im_addr_nxt, w3_im_data, w3_im_data_nxt, w4_im_notused, w4_im_notused_nxt : gp_register_t;
+signal new_im_data, new_im_data_nxt: std_logic;
+
+begin
+
+
+syn : process (clk, reset)
+begin
+ if (reset = RESET_VALUE) then
+ w1_st_co <= (others=>'0');
+ w2_im_addr(31 downto 16) <= (others=>'0');
+ -- todo mit einer konstante versehen
+ w2_im_addr(15 downto 0) <= x"0004";
+ w3_im_data <= (others=>'0');
+ w4_im_notused <= (others=>'0');
+ --im only
+ new_im_data <= '0';
+
+
+ elsif rising_edge(clk) then
+ w1_st_co <= w1_st_co_nxt;
+ w2_im_addr <= w2_im_addr_nxt;
+ w3_im_data <= w3_im_data_nxt;
+ w4_im_notused <= w4_im_notused_nxt;
+ --im only
+ new_im_data <= new_im_data_nxt;
+
+ end if;
+end process syn;
+
+-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
+
+gwriten : process (ext_reg,w1_st_co,w2_im_addr,w3_im_data,w4_im_notused)
+
+variable tmp_data : gp_register_t;
+
+begin
+
+ w1_st_co_nxt <= w1_st_co;
+ w2_im_addr_nxt <= w2_im_addr;
+ w3_im_data_nxt <= w3_im_data;
+ w4_im_notused_nxt <= w4_im_notused;
+
+ if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+
+ case ext_reg.addr(1 downto 0) is
+ when "00" =>
+ w1_st_co_nxt <= tmp_data;
+ when "01" =>
+ -- -1 wegen increment des addr registers
+ tmp_data := tmp_data - '1';
+ w2_im_addr_nxt <= tmp_data;
+ when "10" =>
+ w1_st_co_nxt(16) <= '1'; -- busy flag set
+ w2_im_addr_nxt <= w2_im_addr + '1';
+ w3_im_data_nxt <= tmp_data;
+ when "11" =>
+ --w4_im_notused_nxt <= tmp_data; sollte nur gelesen werden
+ when others => null;
+ end case;
+ end if;
+
+end process gwriten;
+
+gread : process (clk,ext_reg,w1_st_co,w2_im_addr,w3_im_data,w4_im_notused)
+
+variable tmp_data : gp_register_t;
+
+begin
+ if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
+ case ext_reg.addr(1 downto 0) is
+ when "00" =>
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w1_st_co(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ data_out <= tmp_data;
+ when "01" =>
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w2_im_addr(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_im_addr((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_im_addr((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_im_addr((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ data_out <= tmp_data;
+ when "10" =>
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w3_im_data(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_im_data((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_im_data((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_im_data((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ data_out <= tmp_data;
+ when "11" =>
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w4_im_notused(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_im_notused((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_im_notused((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_im_notused((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ data_out <= tmp_data;
+ when others => null;
+ end case;
+ else
+ data_out <= (others=>'0');
+ end if;
+end process gread;
+
+
+-------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
+
+-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
+
+dataprocess : process (ext_reg)
+
+
+begin
+new_im_data_nxt <= '0';
+if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
+ case ext_reg.addr(1 downto 0) is
+ when "00" =>
+
+ when "01" =>
+
+ when "10" =>
+ new_im_data_nxt <= '1';
+ when "11" =>
+
+ when others => null;
+ end case;
+ end if;
+
+end process dataprocess;
+-- asyncrone verarbeitung
+im_addr <= w2_im_addr;
+im_data <= w3_im_data;
+new_im_data_out <= new_im_data;
+
+
+
+
+-------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
+
+end behav;
+
--- /dev/null
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+
+package extension_imp_pkg is
+
+ component extension_imp is
+ --some modules won't need all inputs/outputs
+ generic (
+ -- active reset value
+ RESET_VALUE : std_logic
+ );
+ port(
+ --System inputs
+ clk : in std_logic;
+ reset : in std_logic;
+ -- general extension interface
+ ext_reg : in extmod_rec;
+ data_out : out gp_register_t;
+ -- Input
+
+ -- Ouput
+ im_addr : out gp_register_t;
+ im_data : out gp_register_t;
+ new_im_data_out : out std_logic
+ );
+ end component extension_imp;
+
+
+end package extension_imp_pkg;
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+
+entity extension_interrupt is
+ --some modules won't need all inputs/outputs
+ generic (
+ -- active reset value
+ RESET_VALUE : std_logic
+ );
+ port(
+ --System inputs
+ clk : in std_logic;
+ reset : in std_logic;
+ -- general extension interface
+ ext_reg : in extmod_rec;
+ data_out : out gp_register_t;
+ -- Input
+ uart_int : in std_logic;
+ -- Ouput
+ int_req : out interrupt_t
+ );
+ end extension_interrupt;
+
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_pkg.all;
+
+architecture behav of extension_interrupt is
+
+signal w1_st_co, w1_st_co_nxt, w2_int_config, w2_int_config_nxt : gp_register_t;
+
+begin
+
+syn : process (clk, reset)
+begin
+ if (reset = RESET_VALUE) then
+ w1_st_co <= (others=>'0');
+ w2_int_config(31 downto 0) <= (others=>'0');
+ -- todo mit einer konstante versehen
+
+ elsif rising_edge(clk) then
+ w1_st_co <= w1_st_co_nxt;
+ w2_int_config <= w2_int_config_nxt;
+ end if;
+end process syn;
+
+-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
+
+gwriten : process (ext_reg,w1_st_co,w2_int_config)
+
+variable tmp_data : gp_register_t;
+
+begin
+
+ w1_st_co_nxt <= w1_st_co;
+ w2_int_config_nxt <= w2_int_config;
+
+ if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) :=ext_reg.data(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := ext_reg.data((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := ext_reg.data((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := ext_reg.data((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+
+ case ext_reg.addr(1 downto 0) is
+ when "00" =>
+ w1_st_co_nxt <= tmp_data;
+ when "01" =>
+ w2_int_config_nxt <= tmp_data;
+ when others => null;
+ end case;
+ end if;
+
+end process gwriten;
+
+gread : process (clk,ext_reg,w1_st_co,w2_int_config)
+
+variable tmp_data : gp_register_t;
+
+begin
+
+ if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
+ case ext_reg.addr(1 downto 0) is
+ when "00" =>
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w1_st_co(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ data_out <= tmp_data;
+ when "01" =>
+ tmp_data := (others =>'0');
+ if ext_reg.byte_en(0) = '1' then
+ tmp_data(byte_t'range) := w2_int_config(byte_t'range);
+ end if;
+ if ext_reg.byte_en(1) = '1' then
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_int_config((2*byte_t'length-1) downto byte_t'length);
+ end if;
+ if ext_reg.byte_en(2) = '1' then
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_int_config((3*byte_t'length-1) downto 2*byte_t'length);
+ end if;
+ if ext_reg.byte_en(3) = '1' then
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_int_config((4*byte_t'length-1) downto 3*byte_t'length);
+ end if;
+ data_out <= tmp_data;
+ when others => data_out <= (others => '0');
+ end case;
+ else
+ data_out <= (others=>'0');
+ end if;
+end process gread;
+
+
+-------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
+
+-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
+
+dataprocess : process (w2_int_config, uart_int)
+
+begin
+
+ int_req <= IDLE;
+
+ if (w2_int_config(GLOBAL_INT_EN_BIT) = '1') then
+ if (w2_int_config(UART_INT_EN_BIT) = '1' and uart_int = '1') then
+ int_req <= UART;
+ end if;
+ end if;
+
+end process dataprocess;
+
+
+
+-------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
+
+end behav;
+
type extmod_rec is record
sel : std_logic;
wr_en : std_logic;
- byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0);
+ byte_en : byte_en_t;
data : gp_register_t;
addr : ext_addr_t;
end record;
carry : std_logic;
end record;
-constant EXT_7SEG_ADDR: ext_addrid_t := x"FFFFFFA";
+constant EXT_7SEG_ADDR: ext_addrid_t := x"0000201";
constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
constant EXT_TIMER_ADDR: ext_addrid_t := x"FFFFFFC";
constant EXT_AC97_ADDR: ext_addrid_t := x"FFFFFFD";
---constant EXT_UART_ADDR: ext_addrid_t := x"FFFFFFE";
-constant EXT_UART_ADDR: ext_addrid_t := x"0000000";
+-- constant EXT_UART_ADDR: ext_addrid_t := x"FFFFFFE";
+constant EXT_UART_ADDR: ext_addrid_t := x"0000200";
+constant EXT_INT_ADDR: ext_addrid_t := x"0000202";
+constant EXT_IMP_ADDR: ext_addrid_t := x"0000203";
constant EXT_GPMP_ADDR: ext_addrid_t := x"FFFFFFF";
- component extension_gpm is
+component extension_gpm is
--some modules won't need all inputs/outputs
generic (
-- active reset value
);
end component extension_gpm;
+component extension_interrupt is
+ --some modules won't need all inputs/outputs
+ generic (
+ -- active reset value
+ RESET_VALUE : std_logic
+ );
+ port(
+ --System inputs
+ clk : in std_logic;
+ reset : in std_logic;
+ -- general extension interface
+ ext_reg : in extmod_rec;
+ data_out : out gp_register_t;
+ -- Input
+ uart_int : in std_logic;
+ -- Ouput
+ int_req : out interrupt_t
+ );
+ end component extension_interrupt;
end package extension_pkg;
-- general extension interface
ext_reg : in extmod_rec;
data_out : out gp_register_t;
- -- Input
+ uart_int : out std_logic;
+ -- Input
+ bus_rx : in std_logic;
-- Ouput
bus_tx : out std_logic
);
architecture behav of extension_uart is
signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
-signal new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
+signal new_bus_rx,new_wb_data, new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
signal bd_rate : baud_rate_l;
+signal rx_data : std_logic_vector(7 downto 0);
+
+signal uart_int_nxt : std_logic;
+
+signal uart_data_read, uart_data_read_nxt : std_logic;
begin
w1_st_co(0)
);
+rs232_rx_inst : rs232_rx
+generic map(
+ RESET_VALUE,
+ 2
+ )
+port map(
+ --System inputs
+ clk,
+ reset,
+
+ --Bus
+ bus_rx,
+
+ --From/to sendlogic
+ new_bus_rx,
+ rx_data,
+ bd_rate
+);
syn : process (clk, reset)
begin
- if (reset = RESET_VALUE) then
- w1_st_co <= (others=>'0');
- w2_uart_config <= (others=>'0');
- w3_uart_send <= (others=>'0');
- w4_uart_receive <= (others=>'0');
-
-
- elsif rising_edge(clk) then
- w1_st_co <= w1_st_co_nxt;
- w2_uart_config <= w2_uart_config_nxt;
- w3_uart_send <= w3_uart_send_nxt;
- w4_uart_receive <= w4_uart_receive_nxt;
- new_tx_data <= new_tx_data_nxt;
- tx_rdy_int <= tx_rdy;
- end if;
+ if (reset = RESET_VALUE) then
+ w1_st_co <= (others=>'0');
+ w2_uart_config(31 downto 16) <= (others=>'0');
+ -- todo mit einer konstante versehen
+ w2_uart_config(15 downto 0) <= x"01B2";
+ w3_uart_send <= (others=>'0');
+ w4_uart_receive <= (others=>'0');
+ tx_rdy_int <= '0';
+ new_tx_data <= '0';
+ uart_data_read <= '0';
+ uart_int <= '0';
+
+ elsif rising_edge(clk) then
+ w1_st_co <= w1_st_co_nxt;
+ w2_uart_config <= w2_uart_config_nxt;
+ w3_uart_send <= w3_uart_send_nxt;
+ w4_uart_receive <= w4_uart_receive_nxt;
+ new_tx_data <= new_tx_data_nxt;
+ tx_rdy_int <= tx_rdy;
+ uart_data_read <= uart_data_read_nxt;
+ uart_int <= uart_int_nxt;
+ end if;
end process syn;
-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
-gwriten : process (ext_reg,tx_rdy)
+gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read)
variable tmp_data : gp_register_t;
begin
+ uart_int_nxt <= '0';
+ w1_st_co_nxt <= w1_st_co;
+ w2_uart_config_nxt <= w2_uart_config;
+ w3_uart_send_nxt <= w3_uart_send;
+ w4_uart_receive_nxt <= w4_uart_receive;
+
if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
tmp_data := (others =>'0');
if ext_reg.byte_en(0) = '1' then
w1_st_co_nxt(16) <= '1'; -- busy flag set
w3_uart_send_nxt <= tmp_data;
when "11" =>
- w4_uart_receive_nxt <= tmp_data;
+ --w4_uart_receive_nxt <= tmp_data; sollte nur gelesen werden
when others => null;
end case;
- else
- w1_st_co_nxt <= w1_st_co;
- w2_uart_config_nxt <= w2_uart_config;
- w3_uart_send_nxt <= w3_uart_send;
- w4_uart_receive_nxt <= w4_uart_receive;
end if;
if tx_rdy = '1' and tx_rdy_int = '0' then
w1_st_co_nxt(16) <= '0'; -- busy flag reset
end if;
+ if new_bus_rx = '1' then
+ w4_uart_receive_nxt(7 downto 0) <= rx_data;
+ w1_st_co_nxt(17) <= '1';
+ uart_int_nxt <= '1';
+ end if;
+
+ if (uart_data_read = '1' and w1_st_co(17) = '1' and ext_reg.sel = '1') then
+ w1_st_co_nxt(17) <= '0';
+ end if;
+
end process gwriten;
-gread : process (clk,ext_reg)
+gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
variable tmp_data : gp_register_t;
begin
+
+ uart_data_read_nxt <= '0';
+
if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
case ext_reg.addr(1 downto 0) is
when "00" =>
end if;
data_out <= tmp_data;
when "11" =>
- tmp_data := (others =>'0');
+ tmp_data := (others =>'0');
+ uart_data_read_nxt <= '1';
if ext_reg.byte_en(0) = '1' then
tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
end if;
-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
-dataprocess : process (ext_reg,tx_rdy)
+dataprocess : process (ext_reg,tx_rdy,w2_uart_config)
begin
--RS232
constant UART_WIDTH : integer := 8;
subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
-constant BAUD_RATE_WITH : integer := 16;
-subtype baud_rate_l is std_logic_vector(BAUD_RATE_WITH-1 downto 0);
+constant BAUD_RATE_WIDTH : integer := 16;
+subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
--CLKs
-constant CLK_FREQ_MHZ : real := 33.33;
-constant BAUD_RATE : integer := 115200;
-constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
+--constant CLK_FREQ_MHZ : real := 33.33;
+--constant BAUD_RATE : integer := 115200;
+--constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
+constant CLK_PER_BAUD : integer := 434;
component extension_uart is
--some modules won't need all inputs/outputs
-- general extension interface
ext_reg : in extmod_rec;
data_out : out gp_register_t;
- -- Input
+ uart_int : out std_logic;
+ -- Input
+ bus_rx : in std_logic;
-- Ouput
bus_tx : out std_logic
);
);
end component rs232_tx;
+component rs232_rx is
+ generic (
+ -- active reset value
+ RESET_VALUE : std_logic;
+ SYNC_STAGES : integer range 2 to integer'high
+ );
+
+ port(
+ --System inputs
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+
+ --Bus
+ bus_rx_unsync : in std_logic;
+
+ --To sendlogic
+ new_rx_data : out std_logic;
+ rx_data : out uart_data;
+ bd_rate : in baud_rate_l
+ );
+end component rs232_rx;
+
+
+
end package extension_uart_pkg;
prediction_result : in instruction_addr_t;
branch_prediction_bit : in std_logic;
alu_jump_bit : in std_logic;
+ int_req : in interrupt_t;
+ -- instruction memory program port :D
+ new_im_data_in : in std_logic;
+ im_addr : in gp_register_t;
+ im_data : in gp_register_t;
--Data outputs
instruction : out instruction_word_t;
signal instr_r_addr_nxt : instruction_addr_t;
signal instr_we : std_logic;
signal instr_wr_data : instruction_word_t;
-signal instr_rd_data : instruction_word_t;
+signal instr_rd_data_rom, instr_rd_data : instruction_word_t;
+signal rom_ram, rom_ram_nxt : std_logic;
begin
- instruction_ram : r_w_ram
+ instruction_ram : r_w_ram --rom
generic map (
PHYS_INSTR_ADDR_WIDTH,
WORD_WIDTH
port map (
clk,
- instr_w_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
+ im_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
instr_r_addr_nxt(PHYS_INSTR_ADDR_WIDTH-1 downto 0),
- instr_we,
- instr_wr_data,
+ new_im_data_in,
+ im_data,
instr_rd_data
);
+
+ instruction_rom : rom
+ generic map (
+ ROM_INSTR_ADDR_WIDTH,
+ WORD_WIDTH
+ )
+
+ port map (
+ clk,
+ instr_r_addr_nxt(ROM_INSTR_ADDR_WIDTH-1 downto 0),
+ instr_rd_data_rom
+ );
+
syn: process(clk, reset)
if (reset = RESET_VALUE) then
instr_r_addr <= (others => '0');
+ rom_ram <= ROM_USE;
elsif rising_edge(clk) then
instr_r_addr <= instr_r_addr_nxt;
+ rom_ram <= rom_ram_nxt;
end if;
end process;
-asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
+asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
begin
-
- instruction <= instr_rd_data;
+ rom_ram_nxt <= rom_ram;
+
+ case rom_ram is
+ when ROM_USE =>
+ instruction <= instr_rd_data_rom;
+ when RAM_USE =>
+ instruction <= instr_rd_data;
+ when others =>
+ instruction <= x"F0000000";
+ end case;
instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
+ if (instr_r_addr(ROM_INSTR_ADDR_WIDTH) = '1' and rom_ram = ROM_USE) then
+ rom_ram_nxt <= RAM_USE;
+ instr_r_addr_nxt <= (others => '0');
+ end if;
+
if (reset = RESET_VALUE) then
instr_r_addr_nxt <= (others => '0');
end if;
- if (alu_jump_bit = LOGIC_ACT) then
+ if (alu_jump_bit = LOGIC_ACT and int_req = IDLE) then
instr_r_addr_nxt <= jump_result;
instruction(31 downto 28) <= "1111";
elsif (branch_prediction_bit = LOGIC_ACT) then
instr_r_addr_nxt <= prediction_result;
end if;
+ case int_req is
+ when UART =>
+ instruction(31 downto 0) <= (others => '0');
+ instruction(31 downto 28) <= "1110";
+ instruction(27 downto 23) <= "10110";
+ instruction(PHYS_INSTR_ADDR_WIDTH + 7 - 1 downto 7) <= UART_INT_VECTOR;
+ instruction(6 downto 4) <= "001";
+ instruction(3 downto 2) <= "01";
+ instruction(1 downto 0) <= "10";
+
+-- instr_r_addr_nxt <= instr_r_addr;
+ when others => null;
+ end case;
+
end process;
-prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
-prog_cnt(31 downto 11) <= (others => '0');
+out_logic : process (instr_r_addr, alu_jump_bit, int_req, jump_result)
+
+begin
+ prog_cnt(10 downto 0) <= std_logic_vector(unsigned(instr_r_addr(PHYS_INSTR_ADDR_WIDTH-1 downto 0)));
+ prog_cnt(31 downto 11) <= (others => '0');
+
+ if (int_req /= IDLE and alu_jump_bit = LOGIC_ACT ) then
+ prog_cnt(10 downto 0) <= jump_result(10 downto 0);
+ end if;
+
+end process;
end behav;
data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component r_w_ram;
+
+ component r_w_ram_be is
+ generic (
+ ADDR_WIDTH : integer range 1 to integer'high
+ );
+ port(
+ clk : in std_logic;
+
+ waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+ be : in std_logic_vector (3 downto 0);
+
+ we : in std_logic;
+
+ wdata : in std_logic_vector(31 downto 0);
+
+ q : out std_logic_vector(31 downto 0)
+ );
+ end component r_w_ram_be;
+
+ component ram_xilinx is
+ generic ( ADDR_WIDTH : integer range 1 to integer'high);
+ port(clk : in std_logic;
+ addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+ be : in std_logic_vector(3 downto 0);
+ we : in std_logic; -- dummy :/
+ wdata : in std_logic_vector(31 downto 0);
+ q : out std_logic_vector(31 downto 0)
+ );
+ end component ram_xilinx;
+
+ component rom is
+ generic (
+ ADDR_WIDTH : integer range 1 to integer'high;
+ DATA_WIDTH : integer range 1 to integer'high
+ );
+ port(
+ --System inputs
+ clk : in std_logic;
+ --Input
+ rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+ --Output
+ data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
+ );
+ end component rom;
component r2_w_ram is
generic (
-------------------------------------------------------------------------------
architecture behavior of pipeline_tb is
- constant cc : time := 30 ns; -- test clock period
-
+ constant cc : time := 20 ns; -- test clock period
+ constant SYS_CLOCK_FREQ : integer := 50000000;
+ constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200;
+
signal sys_clk_pin : std_logic;
signal sys_res_n_pin : std_logic;
--Data input
signal dmem_pin : std_logic;--memop
signal dmem_wr_en_pin : std_logic;
signal hword_pin : std_logic;
- signal byte_s_pin : std_logic;
+ signal byte_s_pin, tx_pin, rx_pin : std_logic;
signal gpm_in_pin : extmod_rec;
signal gpm_out_pin : gp_register_t;
signal cycle_cnt : integer;
+ signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
+ signal int_req_pin : interrupt_t;
+
+ signal new_im_data :std_logic;
+ signal im_addr, im_data : gp_register_t;
begin
prediction_result => prediction_result_pin, --: in instruction_addr_t;
branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+ new_im_data_in => new_im_data,
+ im_addr => im_addr,
+ im_data => im_data,
--Data outputs
instruction => instruction_pin, --: out instruction_word_t
- prog_cnt => prog_cnt
+ prog_cnt => prog_cnt,
+ int_req => int_req_pin
);
decode_st : decode_stage
data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
writeback_st : writeback_stage
- generic map('0', '1')
+ generic map('0', '1', "altera")
port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);
wait until sys_clk_pin = '1' and sys_clk_pin'event;
end loop;
end;
+
+ procedure txd(trans_data : in std_logic_vector) is
+ begin
+ for i in 0 to 9 loop
+ rx_pin <= trans_data(i);
+ dummy <= not dummy;
+ wait on dummy;
+ icwait(BAUD_COUNT);
+ end loop;
+ end txd;
+
begin
-----------------------------------------------------------------------------
sys_res_n_pin <= '1';
wait until sys_res_n_pin = '1';
+ icwait(10);
+
+ txd("0100000101");
- icwait(100000);
+ icwait(1000000000);
---------------------------------------------------------------------------
-- exit testbench
subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
- -- r0 = 0, r1 = 1, r2 = 3, r3 = A
-
- signal ram : RAM_TYPE := (
-
-
- 0 => "11101101000000000000000001011000", -- r0 = 11
- 1 => "11101101000010000000000000111000", -- r1 = 7
- 2 => "11100111100010000000000000000000", --stw
- 3 => "11101101000000000000000000011000", -- r0 = 3
- 4 => "11101101000010000000000001001000", -- r1 = 9
- 5 => "11100111000010000000000000000000", --ldw
- 6 => "11101101000000000000000000011000", -- r0 = 3
- 7 => "11101101000010000000000001001000", -- r1 = 9
- --8 => "11100111100010000000000000000000", --stw
--- 0 => "11101101000000000000000000000000", --ldi
--- 1 => "11101101001000000000000000000000", --ldi
--- 2 => "11100111101000000000000000000000", --stw
--- 3 => "11100001000000000000000000100001",
--- 4 => "11101100100000000000001100000000",
--- 5 => "00001011011111111111111010000011",
--- 6 => "11101101000000000000000000001000",
--- 7 => "11100111100000000000000000001111",
--- 8 => "11100111100000000000000000010011",
-
--- 9 => x"ed080048", --;ldi r1, 9;;
--- 10 => x"ed500080", --;ldil r10, list@lo ;; global pointer
--- 11 => x"fd500002", --;ldih r10, list@hi;;
--- 12 => x"eb000107", --;call+ fibcall;;
- --13 => x"eb7ffe03", --;br+ main;;
--- 13 => "11101011000000000000000000000010", -- endless loop --2; fib(n) {
- --2; if (list[n] > 0) {
- --2; return list[n]
- --2; }
- --2; a = fib(n-1)
- --2; list[n] = a + list[n-2]
- --2; return list[n]
- --2; }
- --3;fibcall;
- --2;update counter for aligned access
--- 14 => x"e5088800", --;lls r1, r1, 2 ;; *4
- --2;calculate adress of top element
--- 15 => x"e0150800", --;add r2, r10, r1;;
- --3;fibmem;
- --2;load top element
--- 16 => x"e7010000", --;ldw r0, 0(r2);;
- --2;compare if set
--- 17 => x"ec800000", --;cmpi r0, 0;;
- --2;return if set
--- 18 => x"0b000008", --;retnz-;;
- --2;decrement adress for next lopp
--- 19 => x"e1910020", --;subi r2, r2, 4;;
- --2;iterative call for n-1 element
--- 20 => x"eb7ffe07", --;call+ fibmem;;
- --2;load n-2 element
--- 21 => x"e7197ffc", --;ldw r3, 0-4(r2);;
- --2;add n-1 and n-2 element
--- 22 => x"e0018000", --;add r0, r3, r0;;
- --2;increment address for n element
- --2;is needed because after return
- --2;we need r2 to be set to the address
- --2;of element n
--- 23 => x"e1110020", --;addi r2, r2, 4;;
- --2;store fib n
--- 24 => x"e7810000", --;stw r0, 0(r2);;
--- 25 => x"eb00000a", --;ret+;;
-
--- 1 1 2 3 5 8 13 21 34 55
-
-
- others => x"F0000000");
-
--- signal ram : RAM_TYPE := ( 0 => "11101101000000000000000000000000", -- r0 = 0
---
--- 1 => "11101101000010000000000000111000", -- r1 = 7
--- 2 => "11101101000100000000000000101000", -- r2 = 5
--- 3 => "11101101000110000000000000100000", -- r3 = 4
--- 4 => "11100000001000010001100000000000", -- r4 = r2 + r3
--- 5 => "11100010001010100000100000000000", -- r5 = r4 and r1
---
--- 6 => "11100001000000000000000000001000", -- r0 = r0 + 1
--- 7 => "11101100100000000000000000011000", -- cmpi r0 , 2
---
--- 8 => "00001011011111111111110010000111", -- jump -7
--- 9 => "11101011000000000000000010000010", -- jump +1
--- --10 => "11101011000000000000000010000010", -- jump +1
---
- -- 10 => "11100111101010100000000000000001", -- stw r5,r4,1
- -- 11 => "11101100001000100000000000000000", -- cmp r4 , r4 => 2-2 => 1001
---
--- 12 => "11101011000000000000000000000010", -- jump +0
-
-
-
-
--- others => x"F0000000");
-
--- signal ram : RAM_TYPE := ( 0 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1
--- 1 => "11100000000110001000000000000000", --add r3, r1, r0 => r3 = 1
--- 2 => "11100000001000011001000000000000", --add r4, r3, r2 => r4 = 2
--- 3 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1
--- 4 => "11100000000110001000000000000000", --add r3, r1, r0 => r3 = 1
--- 5 => "11100000001000011001000000000000", --add r4, r3, r2 => r4 = 2
--- 6 => "11101100000000001000000000000000", --cmp r0 , r1 => 0-1 => 0100
--- 7 => "00000000001010101010000000000001", --addnqd r5, r5, r4 => r5 = 2
--- 8 => "00000000001010101010000000000000", --addnq r5, r5, r4 => r5 = 4
--- 9 => "11101100001000100000000000000000", --cmp r4 , r4 => 2-2 => 1001
--- 10 => "00000001001100001000000001010000", --addinq r6, r1, 0xA => nix
--- 11 => "00010001001100001000000001010000", --addieq r6, r1, 0xA => r6 = 0xB
--- 12 => "00010001101100110000000001010000", --subieq r6, r5, 0xA => r6 = 1
--- 13 => "11100000000100001000000000000000", --add r2, r1, r0 => r2 = 1
--- 14 => "11100010000100001000000000000000", --and r2, r1, r0 => r2 = 0
--- 15 => "11101100000000001000000000000000", --cmp r0 , r1 => 0-1 => 0100
--- 16 => "10000000001010101010000000000001", --addabd r5, r5, r4 => r5 = 6
--- 17 => "10110011101110001000010000110001", --orxltd r7, 1086 => r7 = 1086
--- 18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1 => r7 = 2
--- 19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2 => r7 = 4
--- others => x"F0000000");
-
-
+ signal ram : RAM_TYPE := (others => x"00000000");
+
begin
process(clk)
begin
if rising_edge(clk) then
- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+ data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+
+
if wr_en = '1' then
ram(to_integer(UNSIGNED(wr_addr))) <= data_in;
end if;
end if;
end process;
+
end architecture behaviour;
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity r_w_ram_be is
+ generic (
+ ADDR_WIDTH : integer range 1 to integer'high
+ );
+ port(
+ clk : in std_logic;
+
+ waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+ be : in std_logic_vector (3 downto 0);
+
+ we : in std_logic;
+
+ wdata : in std_logic_vector(31 downto 0);
+
+ q : out std_logic_vector(31 downto 0)
+ );
+
+end entity r_w_ram_be;
--- /dev/null
+library ieee;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.mem_pkg.all;
+
+architecture behaviour of r_w_ram_be is
+
+ type word_t is array (0 to 3) of std_logic_vector(7 downto 0);
+ type ram_t is array (0 to (2**ADDR_WIDTH)-1) of word_t;
+ signal ram : ram_t := (others => ((x"00"), (x"00"), (x"00"), (x"00")));
+ signal q_local : word_t;
+
+begin -- Re-organize the read data from the RAM to match the output
+ unpack: for i in 0 to 3 generate
+ q(8*(i+1) - 1 downto 8*i) <= q_local(i);
+ end generate unpack;
+
+ process(clk)
+ begin
+ if(rising_edge(clk)) then
+ if(we = '1') then
+ if(be(0) = '1') then
+ ram(to_integer(UNSIGNED(waddr)))(0) <= wdata(7 downto 0);
+ end if;
+ if be(1) = '1' then
+ ram(to_integer(UNSIGNED(waddr)))(1) <= wdata(15 downto 8);
+ end if;
+ if be(2) = '1' then
+ ram(to_integer(UNSIGNED(waddr)))(2) <= wdata(23 downto 16);
+ end if;
+ if be(3) = '1' then
+ ram(to_integer(UNSIGNED(waddr)))(3) <= wdata(31 downto 24);
+ end if;
+ end if;
+ q_local <= ram(to_integer(UNSIGNED(raddr)));
+ end if;
+ end process;
+
+end architecture behaviour;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+entity ram_xilinx is
+ generic ( ADDR_WIDTH : integer range 1 to integer'high);
+ port(clk : in std_logic;
+ addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+ be : in std_logic_vector(3 downto 0);
+ we : in std_logic; -- dummy :/
+ wdata : in std_logic_vector(31 downto 0);
+ q : out std_logic_vector(31 downto 0)
+ );
+end;
--- /dev/null
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_misc.all;
+use ieee.std_logic_arith.all;
+use ieee.std_logic_unsigned.all;
+library UNISIM;
+use UNISIM.vcomponents.all;
+
+architecture logic of ram_xilinx is
+ constant ZERO : std_logic_vector(31 downto 0) := "00000000000000000000000000000000";
+ constant ONE : std_logic_vector(31 downto 0) := "11111111111111111111111111111111";
+begin
+
+ RAMB16_S9_inst0 : RAMB16_S9 -- 2k x 8bit (+ 1 bit parity)
+ generic map (
+INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
+INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => q(31 downto 24),
+ DOP => open,
+ ADDR => addr(ADDR_WIDTH-1 downto 0),
+ CLK => clk,
+ DI => wdata(31 downto 24),
+ DIP => ZERO(0 downto 0),
+ EN => ONE(0),
+ SSR => ZERO(0),
+ WE => be(3));
+
+ RAMB16_S9_inst1 : RAMB16_S9
+ generic map (
+INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
+INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
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+INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => q(23 downto 16),
+ DOP => open,
+ ADDR => addr(12 downto 2),
+ CLK => clk,
+ DI => wdata(23 downto 16),
+ DIP => ZERO(0 downto 0),
+ EN => ONE(0),
+ SSR => ZERO(0),
+ WE => be(2));
+
+ RAMB16_S9_inst2 : RAMB16_S9
+ generic map (
+INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
+INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => q(15 downto 8),
+ DOP => open,
+ ADDR => addr(12 downto 2),
+ CLK => clk,
+ DI => wdata(15 downto 8),
+ DIP => ZERO(0 downto 0),
+ EN => ONE(0),
+ SSR => ZERO(0),
+ WE => be(1));
+
+ RAMB16_S9_inst3 : RAMB16_S9
+ generic map (
+INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
+INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
+INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000")
+ port map (
+ DO => q(7 downto 0),
+ DOP => open,
+ ADDR => addr(12 downto 2),
+ CLK => clk,
+ DI => wdata(7 downto 0),
+ DIP => ZERO(0 downto 0),
+ EN => ONE(0),
+ SSR => ZERO(0),
+ WE => be(0));
+end;
--- /dev/null
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity rom is
+ generic (
+ ADDR_WIDTH : integer range 1 to integer'high;
+ DATA_WIDTH : integer range 1 to integer'high
+ );
+ port(
+ --System inputs
+ clk : in std_logic;
+ --Input
+ rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+ --Output
+ data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
+ );
+
+end entity rom;
--- /dev/null
+library ieee;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.mem_pkg.all;
+
+architecture behaviour of rom is
+
+ signal vsim_bug : std_logic_vector(31 downto 0);
+
+begin
+ process(clk)
+ begin
+ if rising_edge(clk) then
+-- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+
+
+ --case rrrr_addr(10 downto 0) is
+ case vsim_bug(6 downto 0) is
+ -- fibonacci
+-- when "00000000000" => data_out <= "11101101000000000000000000000000"; --
+-- when "00000000001" => data_out <= "11101101001000000000000000000000"; --
+-- when "00000000010" => data_out <= "11100111101000000000000000000000"; --
+--
+-- when "00000000011" => data_out <= "11100001000000000000000000100001"; --
+-- when "00000000100" => data_out <= "11101100100000000000001100000000"; --
+-- when "00000000101" => data_out <= "00001011011111111111111010000011"; --
+--
+-- when "00000000110" => data_out <= "11101101000000000000000000001000"; --
+-- when "00000000111" => data_out <= "11100111100000000000000000001111"; --
+-- when "00000001000" => data_out <= "11100111100000000000000000010011"; -- --
+--
+--
+-- when "00000001001" => data_out <= x"ed080048"; --x"ed080048"; --
+-- when "00000001010" => data_out <= x"ed500080"; --
+-- when "00000001011" => data_out <= x"fd500002"; --
+-- when "00000001100" => data_out <= x"eb000107";
+-- when "00000001101" => data_out <= "11101011000000000000011010000010"; --"11101011000000000000000000000010";
+--
+-- when "00000001110" => data_out <= x"e5088800";
+-- when "00000001111" => data_out <= x"e0150800";
+-- when "00000010000" => data_out <= x"e7010000";
+-- when "00000010001" => data_out <= x"ec800000";
+-- when "00000010010" => data_out <= x"0b000008";
+-- when "00000010011" => data_out <= x"e1910020";
+-- when "00000010100" => data_out <= x"eb7ffe07";
+-- when "00000010101" => data_out <= x"e7197ffc";
+-- when "00000010110" => data_out <= x"e0018000";
+--
+-- when "00000010111" => data_out <= x"e1110020";
+-- when "00000011000" => data_out <= x"e7810000";
+-- when "00000011001" => data_out <= x"eb00000a";
+--
+--
+-- when "00000011010" => data_out <= x"ed290080";
+-- when "00000011011" => data_out <= x"e1080000";
+--
+-- when "00000011100" => data_out <= x"e78a8000";
+--
+-- when "00000011101" => data_out <= x"ed510058";
+-- when "00000011110" => data_out <= x"e7850000";
+
+ -- uart echo
+
+--1;00000000;ed010058;ldi r0, 0x200B;;
+--1;00000004;ed090060;ldi r1, 0x200C;;
+--1;00000008;ed110080;ldi r2, 0x2010;;
+--1;0000000c;e7188000;ldw r3, 0(r1);;
+--1;00000010;ec1a0000;cmp r3, r4;;
+--1;00000014;1b7ffd81;breq 0;;
+--1;00000018;e7980000;stw r3, 0(r0);;
+--1;0000001c;e7990000;stw r3, 0(r2);;
+--1;00000020;e1218000;addi r4, r3, 0;;
+--1;00000024;eb7ffb81;br 0;;
+
+-- when "0000000" => data_out <= x"ed010058";
+-- when "0000001" => data_out <= x"ed090060";
+-- when "0000010" => data_out <= x"ed110080"; --x"e7188000"; f
+-- when "0000011" => data_out <= x"e7188000"; --x"ec1a0000";
+-- when "0000100" => data_out <= x"ec1a0000";
+-- when "0000101" => data_out <= x"1b7ffe01";
+-- when "0000110" => data_out <= x"e7990000"; -- f
+-- when "0000111" => data_out <= x"e7980000";
+-- when "0001000" => data_out <= x"e1218000";
+-- when "0001001" => data_out <= x"eb7ffb81";
+
+--1;00000000;ed010058;ldi r0, 0x200B;;;
+--1;00000004;ed090060;ldi r1, 0x200C;;;
+--1;00000008;ed110080;ldi r2, 0x2010;;;
+--1;0000000c;ed390078;ldi r7, 0x200F;;;
+--1;00000010;ed480012;ldih r9, 0x0002;;;
+--1;00000014;e7438000;ldw r8, 0(r7);;;
+--1;00000018;e254c000;and r10, r9, r8;;;
+--1;0000001c;07188000;ldwnz r3, 0(r1);;;
+--1;00000020;07980000;stwnz r3, 0(r0);;;
+--1;00000024;07990000;stwnz r3, 0(r2);;;
+--1;00000028;eb7ffb01;br 0;;;
+
+--uart test:
+
+-- when "0000000" => data_out <= x"ed010058";
+-- when "0000001" => data_out <= x"ed090060";
+-- when "0000010" => data_out <= x"ed110080"; --x"e7188000"; f
+-- when "0000011" => data_out <= x"ed390000"; --x"ec1a0000";
+-- when "0000100" => data_out <= x"ed480012";
+-- when "0000101" => data_out <= x"e7438000";
+-- when "0000110" => data_out <= x"e254c000"; -- f
+-- when "0000111" => data_out <= x"07188000";
+-- when "0001000" => data_out <= x"07980000";
+-- when "0001001" => data_out <= x"07990000";
+-- when "0001010" => data_out <= x"eb7ffb81";
+
+-------------------------------------------
+
+-- when "00000000000" => data_out <= x"ed000000";
+-- when "00000000001" => data_out <= x"ed080008";
+-- when "00000000010" => data_out <= x"e9880000"; --x"e7188000"; f
+-- when "00000000011" => data_out <= x"e5088400"; --x"ec1a0000";
+-- when "00000000100" => data_out <= x"e9880001";
+-- when "00000000101" => data_out <= x"e7180000";
+-- when "00000000110" => data_out <= x"e9200001"; -- f
+-- when "00000000111" => data_out <= x"e7a00004";
+-- when "00000001000" => data_out <= x"e7280004";
+-- -- when "00000001001" => data_out <= x"eb7ffb81";
+
+ -- when "0000000" => data_out <= "11101011000000000000010000000010";
+ -- when "0000001" => data_out <= "11101011000000000001000000000110";
+ -- when "0000010" => data_out <= x"eb000008";
+
+ -- when "0001000" => data_out <= x"ed090058";
+ -- when "0001001" => data_out <= x"ed110060";
+ -- when "0001010" => data_out <= x"ed190080";
+ -- when "0001011" => data_out <= x"ed210120";
+ -- when "0001100" => data_out <= x"ed280018";
+ -- when "0001101" => data_out <= x"e7aa0000";
+
+ -- when "0100000" => data_out <= x"f7aa0000";
+ -- when "0100001" => data_out <= x"e7390000";
+ -- when "0100010" => data_out <= x"e13b8008";
+ -- when "0100011" => data_out <= x"e7b98000";
+ -- when "0100100" => data_out <= x"e7b88000";
+ -- when "0100101" => data_out <= x"eb000008";
+
+ when "0000000" => data_out <= x"eb000281";--br 5;;
+ when "0000001" => data_out <= "11101011000000000001000000000110";
+ when "0000010" => data_out <= x"eb000008";
+
+when "0000101" => data_out <= x"ed0101b8";--ldi r0, 0x2037;;
+when "0000110" => data_out <= x"ed0901d8";--ldi r1, 0x203b;;
+when "0000111" => data_out <= x"ed100020";--ldi r2, 4;;
+when "0001000" => data_out <= x"ed180028";--ldi r3, 5;;
+when "0001001" => data_out <= x"e7900000";--stw r2, 0(r0);;
+when "0001010" => data_out <= x"e7988000";--stw r3, 0(r1);;
+
+
+ when others => data_out <= "11101011000000000000000000000010";
+
+ end case;
+ end if;
+ end process;
+
+ vsim_bug(6 downto 0) <= rd_addr;
+ vsim_bug(31 downto 7) <= (others => '0');
+end architecture behaviour;
--- /dev/null
+---------------------------------------------------------------------------------
+-- Filename : rs232_rx.vhd
+-- ==========
+--
+-- Beschreibung : Empfang von Daten ueber die RS232 Schnittstelle
+-- ==============
+--
+-- Autoren : Martin Perner, Schwarz Manfred
+-- =========
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+use work.extension_uart_pkg.all;
+
+entity rs232_rx is
+ generic (
+ -- active reset value
+ RESET_VALUE : std_logic;
+ SYNC_STAGES : integer range 2 to integer'high
+ );
+
+ port(
+ --System inputs
+ sys_clk : in std_logic;
+ sys_res_n : in std_logic;
+
+ --Bus
+ bus_rx_unsync : in std_logic;
+
+ --To sendlogic
+ new_rx_data : out std_logic;
+ rx_data : out uart_data;
+ bd_rate : in baud_rate_l
+ );
+
+end rs232_rx;
--- /dev/null
+---------------------------------------------------------------------------------
+-- Filename : rs232_rx_arc.vhd
+-- ==========
+--
+-- Beschreibung : Empfang von Daten ueber die RS232 Schnittstelle
+-- ==============
+--
+-- Autoren : Martin Perner, Schwarz Manfred
+-- =========
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.extension_uart_pkg.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+architecture beh of rs232_rx is
+ -- definierern der intern verwendeten Signale
+ type STATE_TYPE is (IDLE, READ_START, READ_BIT, READ_STOP, POST_STOP);
+ signal state, state_next : STATE_TYPE;
+ signal bus_rx_last, bus_rx_int, new_rx_data_nxt : std_logic := '0';
+ signal cnt, cnt_next : integer := 0;
+ signal baud_cnt, baud_cnt_next : std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
+ signal rx_data_int, rx_data_nxt, rx_data_res_int, rx_data_res_nxt : uart_data;
+ signal sync : std_logic_vector(1 to SYNC_STAGES);
+ signal bus_rx : std_logic;
+
+begin
+ -- syncronisierungs Prozess
+ rs232_rx_syn : process(sys_clk, sys_res_n)
+ begin
+ if (sys_res_n = RESET_VALUE) then
+ -- reset Zustand
+ state <= IDLE;
+ cnt <= 0;
+ rx_data_res_int <= x"00";
+ baud_cnt <= (others => '0');
+ sync <= (others => '1');
+
+ elsif rising_edge(sys_clk) then
+ -- sync Zustand, uebernehmen der next-Signale
+ state <= state_next;
+ cnt <= cnt_next;
+ baud_cnt <= baud_cnt_next;
+ bus_rx_int <= bus_rx_last;
+ rx_data_int <= rx_data_nxt;
+ rx_data_res_int <= rx_data_res_nxt;
+ new_rx_data <= new_rx_data_nxt;
+
+ sync(1) <= bus_rx_unsync;
+ for i in 2 to SYNC_STAGES loop
+ sync(i) <= sync(i - 1);
+ end loop;
+
+ end if;
+ end process;
+
+ -- setzen des Ausgangsignals, Rxt-Daten
+ rx_data <= rx_data_res_int;
+ bus_rx <= sync(SYNC_STAGES);
+
+ -- Zustandsmaschienen Prozess
+ rs232_states : process(sys_clk,state,cnt, bus_rx, bus_rx_last, baud_cnt,bus_rx_int,bd_rate)
+ begin
+ state_next <= state; -- mal schauen ob des so geht
+ bus_rx_last <= bus_rx; -- mal schauen ob des so geht
+ case state is
+ when IDLE =>
+ -- nach einem Wechsel der rxt-Leitung von 1 auf 0 wird der einlese Vorgang
+ -- getriggert mithilfe eines Zustandsuebergangs von IDLE auf READ_START
+ if (bus_rx_last = '0' and bus_rx_int = '1') then
+ state_next <= READ_START;
+ end if;
+ when READ_START =>
+ -- im READ_START Zustand wird eine halbe Bitzeit gewartet. Liegt auf der rxt-Leitung
+ -- immer noch die 0 an so wird mit deim Lesebvorgang mit einem Zustandswechsel von
+ -- READ_START nach READ_BIT vorgefahren, wenn eine 1 anliegt wird abgebrochen und
+ -- wieder nach IDLE gewechselt
+
+ if (bus_rx = '0' and baud_cnt(BAUD_RATE_WIDTH-2 downto 0) = bd_rate(BAUD_RATE_WIDTH-1 downto 1)) then
+ state_next <= READ_BIT;
+ elsif (bus_rx = '1' and baud_cnt(BAUD_RATE_WIDTH-2 downto 0) = bd_rate(BAUD_RATE_WIDTH-1 downto 1)) then
+ state_next <= IDLE;
+ end if;
+ when READ_BIT =>
+ -- hier werden mit Hilfe eines Countersignals 8 Datenbits im Abstand der eingestellten
+ -- Bitzeit eingelesen und gespeichert.
+ -- Nach beendigung wird in den Zustand READ_STOP gewechselt.
+ if (cnt = 7 and baud_cnt = bd_rate) then
+ state_next <= READ_STOP;
+ else
+ state_next <= READ_BIT;
+ end if;
+ when READ_STOP =>
+ -- hier wird nur noch auf das Stopbit abgewartet und gelesen um den
+ -- Lesevorgang koerrekt zu beenden
+ if baud_cnt = bd_rate and bus_rx = '1' then
+ state_next <= POST_STOP;
+ elsif baud_cnt = bd_rate and bus_rx = '0' then
+ state_next <= IDLE;
+ end if;
+ when POST_STOP =>
+ -- hier wird nur noch eine halbe Bitzeit gewartet
+ if baud_cnt(BAUD_RATE_WIDTH-2 downto 0) = bd_rate(BAUD_RATE_WIDTH-1 downto 1) then
+ state_next <= IDLE;
+ end if;
+ end case;
+ end process;
+
+ -- Ausgabe Logik
+ rs232_rx_baud : process(state, cnt, bus_rx, baud_cnt, rx_data_int, rx_data_res_int, bd_rate)
+ begin
+ -- Signale halten um Latches zu vermeiden
+ cnt_next <= cnt;
+ new_rx_data_nxt <= '0';
+ baud_cnt_next <= baud_cnt;
+ rx_data_nxt <= rx_data_int;
+ rx_data_res_nxt <= rx_data_res_int;
+ -- Statewechesel wie obenbeschrieben
+ case state is
+ when IDLE =>
+ baud_cnt_next <= (others =>'0'); --0;
+ when READ_START =>
+ -- baut_cnt zyklenweise erhoehen bis es einer halben Bitzeit entspricht
+ -- anschliessend zuruecksetzten
+ baud_cnt_next <= std_logic_vector(unsigned(baud_cnt) + 1);
+ if baud_cnt(BAUD_RATE_WIDTH-2 downto 0) = bd_rate(BAUD_RATE_WIDTH-1 downto 1) then
+ baud_cnt_next <= (others => '0');
+ rx_data_nxt <= x"00";
+ end if;
+ when READ_BIT =>
+ -- baut_cnt zyklenweise erhoehen bis es einer Bitzeit entspricht
+ -- anschliessend zuruecksetzen
+ -- Zustand der rxt-Leitung im rx_data_nxt abspeichern
+ baud_cnt_next <= std_logic_vector(unsigned(baud_cnt) + 1);
+ if baud_cnt = bd_rate then
+ baud_cnt_next <= (others => '0');
+ cnt_next <= cnt+1;
+ rx_data_nxt(cnt) <= bus_rx;
+ end if;
+ when READ_STOP =>
+ -- baut_cnt zyklenweise erhoehen bis es einer Bitzeit entspricht
+ -- anschliessend zuruecksetzen
+ -- Counter reseten
+ -- Signal fuer neue rx-Daten setzen um die send_logic zu aktivieren
+ cnt_next <= 0;
+ baud_cnt_next <= std_logic_vector(unsigned(baud_cnt) + 1);
+ if baud_cnt = bd_rate then
+ baud_cnt_next <= (others => '0');
+ end if;
+ when POST_STOP =>
+ --halbe bitzeit wartenr auf counter warten
+ baud_cnt_next <= baud_cnt + 1;
+ if baud_cnt(BAUD_RATE_WIDTH-2 downto 0) = bd_rate(BAUD_RATE_WIDTH-1 downto 1) then
+ new_rx_data_nxt <= '1';
+ rx_data_res_nxt <= rx_data_int;
+ baud_cnt_next <= (others => '0');
+ end if;
+ end case;
+ end process;
+
+end architecture beh;
+
----------------------------------------------------------------------------------\r
--- Filename : rs232_tx_arc.vhd\r
--- ========== \r
--- \r
--- Beschreibung : Versand von Daten ueber die RS232 Schnittstelle\r
--- ==============\r
---\r
--- Autoren : Martin Perner, Schwarz Manfred\r
--- =========\r
-----------------------------------------------------------------------------------\r
-\r
-library IEEE;\r
-use IEEE.std_logic_1164.all;\r
-use IEEE.numeric_std.all;\r
-\r
-use work.common_pkg.all;\r
-use work.core_pkg.all;\r
-use work.extension_uart_pkg.all;\r
-\r
-architecture beh of rs232_tx is\r
- -- definierern der intern verwendeten Signale\r
- type STATE_TYPE is (IDLE,SEND);\r
- signal state, state_next : STATE_TYPE;\r
- signal bus_tx_int, bus_tx_nxt : std_logic := '1';\r
- signal baud_cnt,baud_cnt_next : integer := CLK_PER_BAUD;\r
- signal cnt, cnt_next : natural range 0 to 11 := 0;\r
- signal idle_sig, idle_sig_next : std_logic := '0';\r
- \r
-begin\r
- -- syncronisierungs Prozess\r
- rs232_tx_syn : process(sys_clk, sys_res_n)\r
- begin\r
- if (sys_res_n = RESET_VALUE) then\r
- -- reset\r
- cnt <= 0;\r
- baud_cnt <= 0;\r
- state <= IDLE;\r
- idle_sig <= '0';\r
- bus_tx_int <= '1';\r
- elsif rising_edge(sys_clk) then\r
- -- sync Zustand, uebernehmen der next-Signale\r
- baud_cnt <= baud_cnt_next;\r
- cnt <= cnt_next;\r
- state <= state_next;\r
- idle_sig <= idle_sig_next;\r
- bus_tx_int <= bus_tx_nxt;\r
- end if;\r
- end process;\r
-\r
- bus_tx <= bus_tx_int;\r
-\r
- -- Zustandsmaschienen Prozess\r
- rs232_tx_state : process(state, new_tx_data, idle_sig)\r
- begin\r
- state_next <= state;\r
- case state is\r
- when IDLE =>\r
- -- wenn neue Sendedaten anliegen wird in den Zustand SEND gewechselt\r
- if new_tx_data = '1' then\r
- state_next <= SEND;\r
- end if;\r
- when SEND =>\r
- -- wenn das Byte inklusive Start- und Stopbit versendet wurde, geht \r
- -- der Prozess wieder in den IDLE Zustand.\r
- if idle_sig = '1' then\r
- state_next <= IDLE;\r
- end if;\r
- end case;\r
- end process;\r
-\r
- -- Ausgabe Logik\r
- rs232_tx_baud : process(sys_clk, sys_res_n, state, baud_cnt, cnt, tx_data, bus_tx_int)\r
- begin \r
- -- Solang idle_sig auf 0 ist wird im SEND Zustand verblieben\r
- idle_sig_next <= '0';\r
- bus_tx_nxt <= bus_tx_int;\r
- cnt_next <= cnt;\r
- baud_cnt_next <= baud_cnt;\r
-\r
- case state is\r
- when IDLE =>\r
- -- tx-Signale im idle Zustand halten\r
- tx_rdy <= '1';\r
- baud_cnt_next <= CLK_PER_BAUD;\r
- when SEND =>\r
- -- Signalisiert dass gerade ein Byte versendet wird \r
- tx_rdy <= '0';\r
- -- Counter erhoehen um die Zeit einer Bitdauer abzuwarten\r
- baud_cnt_next <= baud_cnt + 1;\r
- if baud_cnt = CLK_PER_BAUD then \r
- -- wenn die Bitdauer erreicht ist, Counter reseten\r
- baud_cnt_next <= 0;\r
- -- Counter um die einzelen Bits zu versenden\r
- cnt_next <= cnt + 1;\r
- case cnt is\r
- when 0 =>\r
- -- counter = 0 => Startbit versenden\r
- bus_tx_nxt <= '0';\r
- when 9 =>\r
- -- counter = 9 => Stopbit versenden\r
- bus_tx_nxt <= '1';\r
- -- stop_bit 0 heißt 1 stop bit\r
- if stop_bit = '0' then \r
- cnt_next <= 0;\r
- idle_sig_next <= '1';\r
- end if; \r
- when 10 =>\r
- bus_tx_nxt <= '1';\r
- -- stop_bit 1 heißt 2 stop bits\r
- if stop_bit = '1' then \r
- cnt_next <= 0;\r
- -- Signalisieren dass der Sendevorgang beendet ist\r
- idle_sig_next <= '1';\r
- end if;\r
- when others =>\r
- -- counter von 1 bis 8 => Datenbits versenden\r
- bus_tx_nxt <= tx_data(cnt-1);\r
- end case;\r
- end if;\r
- end case;\r
- end process;\r
-\r
-end architecture beh;\r
+---------------------------------------------------------------------------------
+-- Filename : rs232_tx_arc.vhd
+-- ==========
+--
+-- Beschreibung : Versand von Daten ueber die RS232 Schnittstelle
+-- ==============
+--
+-- Autoren : Martin Perner, Schwarz Manfred
+-- =========
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+use work.extension_uart_pkg.all;
+
+architecture beh of rs232_tx is
+ -- definierern der intern verwendeten Signale
+ type STATE_TYPE is (IDLE,SEND);
+ signal state, state_next : STATE_TYPE;
+ signal bus_tx_int, bus_tx_nxt : std_logic := '1';
+ signal baud_cnt,baud_cnt_next : integer := CLK_PER_BAUD;
+ signal cnt, cnt_next : natural range 0 to 11 := 0;
+ signal idle_sig, idle_sig_next : std_logic := '0';
+
+begin
+ -- syncronisierungs Prozess
+ rs232_tx_syn : process(sys_clk, sys_res_n)
+ begin
+ if (sys_res_n = RESET_VALUE) then
+ -- reset
+ cnt <= 0;
+ baud_cnt <= 0;
+ state <= IDLE;
+ idle_sig <= '0';
+ bus_tx_int <= '1';
+ baud_cnt <= 0;
+ elsif rising_edge(sys_clk) then
+ -- sync Zustand, uebernehmen der next-Signale
+ baud_cnt <= baud_cnt_next;
+ cnt <= cnt_next;
+ state <= state_next;
+ idle_sig <= idle_sig_next;
+ bus_tx_int <= bus_tx_nxt;
+ end if;
+ end process;
+
+ bus_tx <= bus_tx_int;
+
+ -- Zustandsmaschienen Prozess
+ rs232_tx_state : process(state, new_tx_data, idle_sig)
+ begin
+ state_next <= state;
+ case state is
+ when IDLE =>
+ -- wenn neue Sendedaten anliegen wird in den Zustand SEND gewechselt
+ if new_tx_data = '1' then
+ state_next <= SEND;
+ end if;
+ when SEND =>
+ -- wenn das Byte inklusive Start- und Stopbit versendet wurde, geht
+ -- der Prozess wieder in den IDLE Zustand.
+ if idle_sig = '1' then
+ state_next <= IDLE;
+ end if;
+ end case;
+ end process;
+
+ -- Ausgabe Logik
+ rs232_tx_baud : process(sys_clk, sys_res_n, state, baud_cnt, cnt, tx_data, bus_tx_int,stop_bit, bd_rate)
+ begin
+ -- Solang idle_sig auf 0 ist wird im SEND Zustand verblieben
+ idle_sig_next <= '0';
+ bus_tx_nxt <= bus_tx_int;
+ cnt_next <= cnt;
+ baud_cnt_next <= baud_cnt;
+
+ case state is
+ when IDLE =>
+ -- tx-Signale im idle Zustand halten
+ tx_rdy <= '1';
+ baud_cnt_next <= CLK_PER_BAUD;
+ when SEND =>
+ -- Signalisiert dass gerade ein Byte versendet wird
+ tx_rdy <= '0';
+ -- Counter erhoehen um die Zeit einer Bitdauer abzuwarten
+ baud_cnt_next <= baud_cnt + 1;
+ if baud_cnt = bd_rate then
+ -- wenn die Bitdauer erreicht ist, Counter reseten
+ baud_cnt_next <= 0;
+ -- Counter um die einzelen Bits zu versenden
+ cnt_next <= cnt + 1;
+ case cnt is
+ when 0 =>
+ -- counter = 0 => Startbit versenden
+ bus_tx_nxt <= '0';
+ when 9 =>
+ -- counter = 9 => Stopbit versenden
+ bus_tx_nxt <= '1';
+ -- stop_bit 0 heit 1 stop bit
+ if stop_bit = '0' then
+ cnt_next <= 0;
+ idle_sig_next <= '1';
+ end if;
+ when 10 =>
+ bus_tx_nxt <= '1';
+ -- stop_bit 1 heit 2 stop bits
+ if stop_bit = '1' then
+ cnt_next <= 0;
+ -- Signalisieren dass der Sendevorgang beendet ist
+ idle_sig_next <= '1';
+ end if;
+ when others =>
+ -- counter von 1 bis 8 => Datenbits versenden
+ bus_tx_nxt <= tx_data(cnt-1);
+ end case;
+ end if;
+ end case;
+ end process;
+
+end architecture beh;
-- active reset value
RESET_VALUE : std_logic;
-- active logic value
- LOGIC_ACT : std_logic
-
+ LOGIC_ACT : std_logic;
+ FPGATYPE : string
);
port(
--System inputs
reg_we : out std_logic;
reg_addr : out gp_addr_t;
jump_addr : out instruction_addr_t;
- jump : out std_logic
+ jump : out std_logic;
+ -- hallo stefan mir adden da jetzt mal schnell an uart port :D
+ bus_tx : out std_logic;
+ bus_rx : in std_logic;
+ -- instruction memory program port :D
+ new_im_data_out : out std_logic;
+ im_addr : out gp_register_t;
+ im_data : out gp_register_t;
+
+ sseg0 : out std_logic_vector(0 to 6);
+ sseg1 : out std_logic_vector(0 to 6);
+ sseg2 : out std_logic_vector(0 to 6);
+ sseg3 : out std_logic_vector(0 to 6);
+
+ int_req : out interrupt_t
+
);
end writeback_stage;
use work.mem_pkg.all;
use work.extension_pkg.all;
use work.extension_uart_pkg.all;
+use work.extension_7seg_pkg.all;
+use work.extension_imp_pkg.all;
architecture behav of writeback_stage is
signal data_ram_read, data_ram_read_ext : word_t;
+signal data_addr : word_t;
signal wb_reg, wb_reg_nxt : writeback_rec;
-signal ext_uart,ext_timer,ext_gpmp : extmod_rec;
+signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int,ext_imp : extmod_rec;
+signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out,ext_imp_out : gp_register_t;
-signal bus_tx,sel_nxt :std_logic;
+--signal int_req : interrupt_t;
+signal uart_int : std_logic;
+signal sel_nxt, dmem_we, ext_anysel : std_logic;
+
+signal calc_mem_res : gp_register_t;
begin
+ ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
+ ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
- data_ram : r_w_ram
+ spartan3e: if FPGATYPE = "s3e" generate
+ data_ram : ram_xilinx
generic map (
- DATA_ADDR_WIDTH,
- WORD_WIDTH
+ DATA_ADDR_WIDTH
+ )
+ port map (
+ clk,
+ data_addr(DATA_ADDR_WIDTH+1 downto 2),
+ wb_reg_nxt.byte_en,
+ dmem_we,
+ wb_reg_nxt.data, --ram_data,
+ data_ram_read
+ );
+ end generate;
+ -- else generate gibt es erst mit vhdl 2008 ...
+ altera: if FPGATYPE /= "s3e" generate
+ data_ram : r_w_ram_be
+ generic map (
+ DATA_ADDR_WIDTH
)
port map (
clk,
- wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
- wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
- wb_reg_nxt.dmem_write_en,
- ram_data,
+ data_addr(DATA_ADDR_WIDTH+1 downto 2),
+ data_addr(DATA_ADDR_WIDTH+1 downto 2),
+ wb_reg_nxt.byte_en,
+ dmem_we,
+ wb_reg_nxt.data, --ram_data,
data_ram_read
);
+ end generate;
uart : extension_uart
generic map(
clk ,
reset,
ext_uart,
- data_ram_read_ext,
+ ext_uart_out,
+ uart_int,
+ bus_rx,
bus_tx
);
+
+imp : extension_imp
+ generic map(
+ RESET_VALUE
+ )
+ port map(
+ clk ,
+ reset,
+ ext_imp,
+ ext_imp_out,
+ im_addr,
+ im_data,
+ new_im_data_out
+ );
+
+ altera_7seg: if FPGATYPE /= "s3e" generate
+sseg : extension_7seg
+ generic map(
+ RESET_VALUE
+ )
+ port map(
+ clk,
+ reset,
+ ext_7seg,
+ sseg0,
+ sseg1,
+ sseg2,
+ sseg3
+ );
+ end generate;
+
+interrupt : extension_interrupt
+ generic map(
+ RESET_VALUE
+ )
+ port map(
+ clk,
+ reset,
+ ext_int,
+ ext_int_out,
+
+ uart_int,
+
+ int_req
+ );
syn: process(clk, reset)
wb_reg.dmem_write_en <= '0';
wb_reg.hword <= '0';
wb_reg.byte_s <= '0';
+
+ wb_reg.byte_en <= (others => '0');
+ wb_reg.data <= (others =>'0');
elsif rising_edge(clk) then
wb_reg <= wb_reg_nxt;
end if;
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en)
-
+shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred, write_en, ram_data)
+variable byte_en : byte_en_t;
+variable address_val : std_logic_vector(1 downto 0);
begin
wb_reg_nxt.address <= address;
wb_reg_nxt.dmem_en <= dmem_en;
wb_reg_nxt.hword <= hword;
wb_reg_nxt.byte_s <= byte_s;
- regfile_val <= result; --(others => '0');
-
- if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
- regfile_val <= data_ram_read;
- if (wb_reg.hword = '1') then
- regfile_val <= (others => '0');
- if (wb_reg.address(1) = '1') then
- regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
- else
- regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
- end if;
- end if;
- if (wb_reg.byte_s = '1') then
- regfile_val <= (others => '0');
- case wb_reg.address(1 downto 0) is
- when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
- when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
- when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
- when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
- when others => null;
+ calc_mem_res <= result; --(others => '0');
+
+ wb_reg_nxt.data <= ram_data;
+ byte_en := (others => '0');
+ address_val := address(BYTEADDR-1 downto 0);
+ if dmem_en = '1' then
+ if hword = '1' then
+-- case address(BYTEADDR-1 downto 0) is
+ case address_val is
+ when "00" =>
+ byte_en(1 downto 0) := "11";
+ when "10" =>
+ byte_en(3 downto 2) := "11";
+ wb_reg_nxt.data(31 downto 16) <= ram_data(15 downto 0);
+ when others => null;
+ end case;
+ elsif byte_s = '1' then
+-- case address(BYTEADDR-1 downto 0) is
+ case address_val is
+ when "00" => byte_en(0) := '1';
+ when "01" =>
+ byte_en(1) := '1';
+ wb_reg_nxt.data(15 downto 8) <= ram_data(7 downto 0);
+ when "10" =>
+ byte_en(2) := '1';
+ wb_reg_nxt.data(23 downto 16) <= ram_data(7 downto 0);
+ when "11" =>
+ byte_en(3) := '1';
+ wb_reg_nxt.data(31 downto 24) <= ram_data(7 downto 0);
+ when others => null;
end case;
- end if;
+ else
+ byte_en := (others => '1');
+ end if;
end if;
+ wb_reg_nxt.byte_en <= byte_en;
+
+ -- if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
+ -- calc_mem_res <= data_ram_read;
+ -- if (wb_reg.hword = '1') then
+ -- calc_mem_res <= (others => '0');
+ -- if (wb_reg.address(1) = '1') then
+ -- calc_mem_res(15 downto 0) <= data_ram_read(31 downto 16);
+ -- else
+ -- calc_mem_res(15 downto 0) <= data_ram_read(15 downto 0);
+ -- end if;
+ -- end if;
+ -- if (wb_reg.byte_s = '1') then
+ -- calc_mem_res <= (others => '0');
+ -- case wb_reg.address(1 downto 0) is
+ -- when "00" => calc_mem_res(7 downto 0) <= data_ram_read(7 downto 0);
+ -- when "01" => calc_mem_res(7 downto 0) <= data_ram_read(15 downto 8);
+ -- when "10" => calc_mem_res(7 downto 0) <= data_ram_read(23 downto 16);
+ -- when "11" => calc_mem_res(7 downto 0) <= data_ram_read(31 downto 24);
+ -- when others => null;
+ -- end case;
+ -- end if;
+ -- end if;
--jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
jump <= (alu_jmp xor br_pred);-- and (write_en or wb_reg.dmem_en);
-- if ((alu_jmp and wb_reg.dmem_en) = '1') then
-- jump_addr <= data_ram_read;
--- end if;
+-- end if;
end process;
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
-
-begin
- reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res, data_ram_read, ext_anysel, result, hword, byte_s)
+variable reg_we_v : std_logic;
+variable data_out : gp_register_t;
+begin
+ reg_we_v := (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
reg_addr <= result_addr;
-end process;
+ data_addr <= (others => '0');
+ dmem_we <= '0';
+
+ if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+ data_out := data_ram_read;
+ else
+ reg_we_v := reg_we_v and ext_anysel;
+ data_out := data_ram_read_ext;
+ end if;
+
+ if wb_reg.byte_en(0) = '0' then
+ data_out(byte_t'range) := (others => '0');
+ end if;
+ if wb_reg.byte_en(1) = '0' then
+ data_out(2*byte_t'length-1 downto byte_t'length) := (others => '0');
+ end if;
+ if wb_reg.byte_en(2) = '0' then
+ data_out(3*byte_t'length-1 downto 2*byte_t'length) := (others => '0');
+ end if;
+ if wb_reg.byte_en(3) = '0' then
+ data_out(4*byte_t'length-1 downto 3*byte_t'length) := (others => '0');
+ end if;
+
+
+-- if wb_reg.hword = '1' or wb_reg.byte_s = '1' then
+-- if wb_reg.address(1)='1' then
+-- data_out(hword_t'range) := data_out(data_out'high downto (data_out'length/2));
+-- end if;
+-- data_out(data_out'high downto (data_out'length/2)) := (others => '0');
+-- if byte_s = '1' then
+-- if wb_reg.address(0) = '1' then
+-- data_out(byte_t'range) := data_out(hword_t'high downto (hword_t'length/2));
+-- end if;
+-- data_out(hword_t'high downto (hword_t'length/2)) := (others => '0');
+-- end if;
+-- end if;
+
+
+ data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length);
+
+ if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
+ data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
+ dmem_we <= wb_reg_nxt.dmem_write_en;
+ end if;
+
+ regfile_val <= data_out;
+
+ if wb_reg.dmem_en = '0' then
+ regfile_val <= result;
+ end if;
+
+ reg_we <= reg_we_v;
+
+end process;
-addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg,sel_nxt,wb_reg_nxt.dmem_write_en)
+addr_de_mult: process(wb_reg, wb_reg_nxt, ram_data, sel_nxt, ext_uart_out, ext_gpmp_out, ext_timer_out)
+variable wr_en, enable : std_logic; -- these are all registered
+variable byte_en : byte_en_t; -- if a module needs the nxt signals it has to manually select them
+variable addr : ext_addr_t; -- for example the data memory, because it already has input registers
+variable addrid : std_logic_vector(27 downto 0);--ext_addrid_t;
+variable data : gp_register_t;
begin
- ext_uart.sel <='0';
- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
- ext_uart.byte_en <= (others => '0');
- ext_uart.data <= (others => '0');
- ext_uart.addr <= (others => '0');
- ext_timer.sel <='0';
- ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
- ext_timer.byte_en <= (others => '0');
- ext_timer.data <= (others => '0');
- ext_timer.addr <= (others => '0');
+ --if selecting enable is too slow, see alu_b
+ enable := wb_reg.dmem_en;
+ wr_en := wb_reg.dmem_write_en;
+ byte_en := wb_reg.byte_en;
+ addr := wb_reg.address(gp_register_t'high downto BYTEADDR);
+ addrid := wb_reg.address(gp_register_t'high downto EXTWORDS);
+ data := wb_reg.data;
+ ext_uart.sel <='0';
+ ext_7seg.sel <='0';
+ ext_timer.sel <='0';
ext_gpmp.sel <='0';
- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
- ext_gpmp.byte_en <= (others => '0');
- ext_gpmp.data <= (others => '0');
- ext_gpmp.addr <= (others => '0');
- -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
- case wb_reg_nxt.address(wb_reg_nxt.address'high downto 4) is
- when EXT_UART_ADDR =>
- ext_uart.sel <='1';
- ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
- ext_uart.data <= ram_data;
- ext_uart.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
- case wb_reg.address(1 downto 0) is
- when "00" => ext_uart.byte_en <= "0001";
- when "01" => ext_uart.byte_en <= "0010";
- when "10" => ext_uart.byte_en <= "0100";
- --when "11" => ext_uart.byte_en <= "1000";
- when "11" => ext_uart.byte_en <= "1111";
- when others => null;
- end case;
+ ext_int.sel <= '0';
+ ext_imp.sel <= '0';
+
+ ext_uart.wr_en <= wr_en;
+ ext_7seg.wr_en <= wr_en;
+ ext_timer.wr_en <= wr_en;
+ ext_gpmp.wr_en <= wr_en;
+ ext_int.wr_en <= wr_en;
+ ext_imp.wr_en <= wr_en;
+
+ ext_uart.byte_en <= byte_en;
+ ext_7seg.byte_en <= byte_en;
+ ext_timer.byte_en <= byte_en;
+ ext_gpmp.byte_en <= byte_en;
+ ext_int.byte_en <= byte_en;
+ ext_imp.byte_en <= byte_en;
+
+ ext_uart.addr <= addr;
+ ext_7seg.addr <= addr;
+ ext_timer.addr <= addr;
+ ext_gpmp.addr <= addr;
+ ext_int.addr <= addr;
+ ext_imp.addr <= addr;
+
+ ext_uart.data <= data;
+ ext_7seg.data <= data;
+ ext_timer.data <= data;
+ ext_gpmp.data <= data;
+ ext_int.data <= data;
+ ext_imp.data <= data;
+
+ -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
+ case addrid is
+ when EXT_UART_ADDR =>
+ ext_uart.sel <= enable;
+ ext_anysel <= enable;
+
+-- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
+-- ext_uart.data <= ram_data;
+-- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
+-- case wb_reg_nxt.address(1 downto 0) is
+-- when "00" => ext_uart.byte_en <= "0001";
+-- when "01" => ext_uart.byte_en <= "0010";
+-- when "10" => ext_uart.byte_en <= "0100";
+-- --when "11" => ext_uart.byte_en <= "1000";
+-- when "11" => ext_uart.byte_en <= "1111";
+-- when others => null;
+-- end case;
+ when EXT_IMP_ADDR =>
+ ext_imp.sel <= enable;
+ ext_anysel <= enable;
+
+-- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
+-- ext_uart.data <= ram_data;
+-- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
+-- case wb_reg_nxt.address(1 downto 0) is
+-- when "00" => ext_uart.byte_en <= "0001";
+-- when "01" => ext_uart.byte_en <= "0010";
+-- when "10" => ext_uart.byte_en <= "0100";
+-- --when "11" => ext_uart.byte_en <= "1000";
+-- when "11" => ext_uart.byte_en <= "1111";
+-- when others => null;
+-- end case;
+
+ when EXT_INT_ADDR =>
+ ext_int.sel <= enable;
+ ext_anysel <= enable;
+
+-- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
+-- ext_uart.data <= ram_data;
+-- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
+-- case wb_reg_nxt.address(1 downto 0) is
+-- when "00" => ext_uart.byte_en <= "0001";
+-- when "01" => ext_uart.byte_en <= "0010";
+-- when "10" => ext_uart.byte_en <= "0100";
+-- --when "11" => ext_uart.byte_en <= "1000";
+-- when "11" => ext_uart.byte_en <= "1111";
+-- when others => null;
+-- end case;
+
+ when EXT_7SEG_ADDR =>
+ ext_7seg.sel <= enable;
+ ext_anysel <= enable;
+
+ -- ext_7seg.wr_en <= wb_regdmem_write_en;
+ -- ext_7seg.data <= ram_data;
+ -- ext_7seg.addr <= wb_reg_nxt.address(31 downto 2);
+ -- ext_7seg.byte_en(1 downto 0) <= wb_reg_nxt.address(1 downto 0);
+
+
+-- case wb_reg_nxt.address(1 downto 0) is
+-- when "00" => ext_7seg.byte_en <= "0001";
+-- when "01" => ext_7seg.byte_en <= "0010";
+-- when "10" => ext_7seg.byte_en <= "0100";
+-- when "11" => ext_7seg.byte_en <= "1000";
+-- when others => null;
+-- end case;
+
when EXT_TIMER_ADDR =>
- ext_timer.sel <='1';
- ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
- ext_timer.data <= ram_data;
- ext_timer.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
- case wb_reg.address(1 downto 0) is
- when "00" => ext_timer.byte_en <= "0001";
- when "01" => ext_timer.byte_en <= "0010";
- when "10" => ext_timer.byte_en <= "0100";
- when "11" => ext_timer.byte_en <= "1000";
- when others => null;
- end case;
+ ext_timer.sel <= enable;
+ ext_anysel <= enable;
+ -- ext_timer.wr_en <= wb_reg_nxt.dmem_write_en;
+ -- ext_timer.data <= ram_data;
+ -- ext_timer.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
+ -- case wb_reg.address(1 downto 0) is
+ -- when "00" => ext_timer.byte_en <= "0001";
+ -- when "01" => ext_timer.byte_en <= "0010";
+ -- when "10" => ext_timer.byte_en <= "0100";
+ -- when "11" => ext_timer.byte_en <= "1000";
+ -- when others => null;
+ -- end case;
when EXT_GPMP_ADDR =>
- ext_gpmp.sel <='1';
- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
- ext_gpmp.data <= ram_data;
- ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
- case wb_reg.address(1 downto 0) is
- when "00" => ext_gpmp.byte_en <= "0001";
- when "01" => ext_gpmp.byte_en <= "0010";
- when "10" => ext_gpmp.byte_en <= "0100";
- when "11" => ext_gpmp.byte_en <= "1000";
- when others => null;
- end case;
+ ext_gpmp.sel <= enable;
+ ext_anysel <= enable;
+ -- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
+ -- ext_gpmp.data <= ram_data;
+ -- ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
+ -- case wb_reg.address(1 downto 0) is
+ -- when "00" => ext_gpmp.byte_en <= "0001";
+ -- when "01" => ext_gpmp.byte_en <= "0010";
+ -- when "10" => ext_gpmp.byte_en <= "0100";
+ -- when "11" => ext_gpmp.byte_en <= "1000";
+ -- when others => null;
+ -- end case;
-- hier kann man weiter extensions adden :) Konstanten sind im extension pkg definiert
- when others => null;
- end case;
-
+ when others => ext_anysel <= '0';
+ end case;
+
+ data_ram_read_ext <= ext_uart_out or ext_gpmp_out or ext_timer_out;
end process;
end behav;
+++ /dev/null
-library IEEE;
-use IEEE.std_logic_1164.all;
-use IEEE.numeric_std.all;
-
-use work.common_pkg.all;
-use work.core_pkg.all;
-
-use work.mem_pkg.all;
-use work.extension_pkg.all;
-
-architecture behav of writeback_stage is
-
-signal data_ram_read : word_t;
-
-signal wb_reg, wb_reg_nxt : writeback_rec;
-signal ext_uart : extmod_rec;
-
-
-
-begin
-
-
- data_ram : r_w_ram
- generic map (
- DATA_ADDR_WIDTH,
- WORD_WIDTH
- )
-
- port map (
- clk,
- wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
- wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 2),
- wb_reg_nxt.dmem_write_en,
- ram_data,
- data_ram_read
- );
-
-
-syn: process(clk, reset)
-
-begin
-
- if (reset = RESET_VALUE) then
- wb_reg.address <= (others => '0');
- wb_reg.dmem_en <= '0';
- wb_reg.dmem_write_en <= '0';
- wb_reg.hword <= '0';
- wb_reg.byte_s <= '0';
- elsif rising_edge(clk) then
- wb_reg <= wb_reg_nxt;
- end if;
-
-end process;
-
--- type writeback_rec is record
--- address : in word_t; --ureg
--- dmem_en : in std_logic; --ureg (jump addr in mem or in address)
--- dmem_write_en : in std_logic; --ureg
--- hword_hl : in std_logic --ureg
--- end record;
-
-
-
-shift_input: process(data_ram_read, address, dmem_en, dmem_write_en, hword, wb_reg, result, byte_s, alu_jmp, br_pred)
-
-begin
- wb_reg_nxt.address <= address;
- wb_reg_nxt.dmem_en <= dmem_en;
- wb_reg_nxt.dmem_write_en <= dmem_write_en;
- wb_reg_nxt.hword <= hword;
- wb_reg_nxt.byte_s <= byte_s;
-
- regfile_val <= result; --(others => '0');
-
- if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
- regfile_val <= data_ram_read;
- if (wb_reg.hword = '1') then
- regfile_val <= (others => '0');
- if (wb_reg.address(1) = '1') then
- regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
- else
- regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
- end if;
- end if;
- if (wb_reg.byte_s = '1') then
- regfile_val <= (others => '0');
- case wb_reg.address(1 downto 0) is
- when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
- when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
- when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
- when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
- when others => null;
- end case;
- end if;
- end if;
-
- jump <= alu_jmp xor br_pred;
- jump_addr <= result;
- if ((alu_jmp and wb_reg.dmem_en) = '1') then
- jump_addr <= data_ram_read;
- end if;
-
-end process;
-
--- result : in gp_register_t; --reg (alu result or jumpaddr)
--- result_addr : in gp_addr_t; --reg
--- address : in word_t; --ureg
--- alu_jmp : in std_logic; --reg
--- br_pred : in std_logic; --reg
--- write_en : in std_logic; --reg (register file)
--- dmem_en : in std_logic; --ureg (jump addr in mem or in result)
--- dmem_write_en : in std_logic; --ureg
--- hword : in std_logic --ureg
-
-
-
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp)
-
-begin
- reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
- reg_addr <= result_addr;
-end process;
-
-
-addr_de_mult: process(address)
-
-begin
-
- ext_uart.sel <='0';
- ext_uart.wr_en <= '0';
- ext_uart.byte_en <= (others => '0');
- ext_uart.data <= (others => '0');
- ext_uart.addr <= (others => '0');
- case wb_reg_nxt.address(wb_reg_nxt.address'high downto EXTWORDS) is
- when EXT_UART_ADDR =>
- ext_uart.sel <='1';
- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
- ext_uart.data <= ram_data;
- ext_uart.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);
- case wb_reg.address(1 downto 0) is
- when "00" => ext_uart.byte_en <= "0001";
- when "01" => ext_uart.byte_en <= "0010";
- when "10" => ext_uart.byte_en <= "0100";
- when "11" => ext_uart.byte_en <= "1000";
- when others => null;
- end case;
-
-
-
- when others => null;
- end case;s
-
-end process;
-
-end behav;
-
--- /dev/null
+ldi r0, 0x200B;;
+ldi r1, 0x200C;;
+ldi r2, 0x2010;;
+ldw r3, 0(r1);;
+cmp r3, r4;;
+breq 4;;
+stw r3, 0(r0);;
+stw r3, 0(r2);;
+addi r4, r3, 0;;
+br 4;;
+
--- /dev/null
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+
+# Quartus II: Generate Tcl File for Project
+# File: dt.tcl
+# Generated on: Mon Dec 20 12:10:32 2010
+
+# Load Quartus II Tcl Project package
+package require ::quartus::project
+
+set need_to_close_project 0
+set make_assignments 1
+
+# Check that the right project is open
+if {[is_project_open]} {
+ if {[string compare $quartus(project) "dt"]} {
+ puts "Project dt is not open"
+ set make_assignments 0
+ }
+} else {
+ # Only open if not already open
+ if {[project_exists dt]} {
+ project_open -revision dt dt
+ } else {
+ project_new -revision dt dt
+ }
+ set need_to_close_project 1
+}
+
+# Make assignments
+if {$make_assignments} {
+ set_global_assignment -name FAMILY Cyclone
+ set_global_assignment -name DEVICE EP1C12Q240C8
+ set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
+ set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:08:54 DECEMBER 16, 2010"
+ set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+ set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+ set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+ set_global_assignment -name GENERATE_RBF_FILE ON
+ set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+ set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+ set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+ set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+ set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+ set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+ set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+ set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+ set_global_assignment -name MISC_FILE /homes/burban/dt/dt.dpf
+ set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+ set_global_assignment -name MISC_FILE /homes/c0726283/calu/dt/dt.dpf
+ set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/rom_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx_arc.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx_arc.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/pipeline_tb.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/mem_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/extension_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/extension_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/extension.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/decoder_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/decoder.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/core_top.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/core_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/common_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/alu_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/alu_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/alu.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/xor_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
+ set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
+ set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+ set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+ set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0
+ set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0
+ set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+ set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+ set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+ set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+ set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
+ set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
+ set_location_assignment PIN_152 -to sys_clk
+ set_location_assignment PIN_42 -to sys_res
+ set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+
+ # Commit assignments
+ export_assignments
+
+ # Close project
+ if {$need_to_close_project} {
+ project_close
+ }
+}
--- /dev/null
+db/
+incremental_db
+work/
+dt.asm.rpt
+dt.done
+dt.dpf
+dt.fit.rpt
+dt.fit.summary
+dt.flow.rpt
+dt.map.rpt
+dt.map.summary
+dt.pin
+dt.pof
+dt.rbf
+dt.sof
+dt.*.rpt
+dt.*.summary
+output_file.pof
+output_file.rbf
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+# Date created = 15:08:54 December 16, 2010
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "10.0"
+DATE = "15:08:54 December 16, 2010"
+
+# Revisions
+
+PROJECT_REVISION = "dt"
--- /dev/null
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions
+# and other software and tools, and its AMPP partner logic
+# functions, and any output files from any of the foregoing
+# (including device programming or simulation files), and any
+# associated documentation or information are expressly subject
+# to the terms and conditions of the Altera Program License
+# Subscription Agreement, Altera MegaCore Function License
+# Agreement, or other applicable license agreement, including,
+# without limitation, that your use is for the sole purpose of
+# programming logic devices manufactured by Altera and sold by
+# Altera or its authorized distributors. Please refer to the
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+# Date created = 15:08:54 December 16, 2010
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+# dt_assignment_defaults.qdf
+# If this file doesn't exist, see file:
+# assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+# file is updated automatically by the Quartus II software
+# and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY Cyclone
+set_global_assignment -name DEVICE EP1C12Q240C8
+set_global_assignment -name TOP_LEVEL_ENTITY core_top
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "15:08:54 DECEMBER 16, 2010"
+set_global_assignment -name LAST_QUARTUS_VERSION "10.0 SP1"
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 240
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name USE_CONFIGURATION_DEVICE ON
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED"
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVCMOS"
+set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
+set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
+set_location_assignment PIN_178 -to bus_tx
+set_location_assignment PIN_152 -to sys_clk
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
+
+
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
+set_global_assignment -name ENABLE_CLOCK_LATENCY ON
+set_global_assignment -name ENABLE_RECOVERY_REMOVAL_ANALYSIS ON
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION ON
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name AUTO_PACKED_REGISTERS_CYCLONE NORMAL
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+set_global_assignment -name MUX_RESTRUCTURE OFF
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_location_assignment PIN_153 -to bus_rx
+set_location_assignment PIN_42 -to sys_res_unsync
+set_global_assignment -name FMAX_REQUIREMENT "50 MHz"
+set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_be.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rom.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rom_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_7seg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx_arc.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rs232_rx.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/writeback_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rw_r_ram.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx_arc.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/rs232_tx.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r_w_ram.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/r2_w_ram.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/pipeline_tb.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/mem_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/fetch_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_uart.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_imp.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_interrupt.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/extension.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/execute_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decoder_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decoder.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/decode_stage.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/core_top.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/core_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/common_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/alu_pkg.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/alu_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/alu.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/xor_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/shift_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/or_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/and_op_b.vhd
+set_global_assignment -name VHDL_FILE ../cpu/src/exec_op/add_op_b.vhd
+
+
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
--- /dev/null
+*.ngc_xst.xrpt
+*.prj
+*.srp
+xst/
+*.bld
+*.ngc
+*_ngdbuild.xrpt
+*.mrp
+*.ncd
+*.ngd
+*.ngm
+*.pad
+*.par
+*.pcf
+*.ptwx
+*.twr
+*.twx
+*.unroutes
+*.xpi
+*_map.xrpt
+*_pad.csv
+*_pad.txt
+*_par.xrpt
+*_summary.xml
+*_usage.xml
+generated/
+smartpreview.twr
+xlnx_auto_0_xdb/
+*.log
+_xmsgs/
--- /dev/null
+run
+-ifn core_top.prj
+-ifmt VHDL
+-ofn core_top.ngc
+-ofmt NGC -p XC3S500E-FG320-4
+-opt_mode Area
+-opt_level 2
--- /dev/null
+setMode -bscan
+setCable -p auto
+identify
+assignFile -p 1 -file generated/core_top.bit
+program -e -p 1
+quit
--- /dev/null
+setMode -bscan
+setCable -p auto
+identify
+assignFile -p 2 -file generated/core_top.mcs
+program -e -p 2 -v
+quit
--- /dev/null
+setMode -pff
+setSubmode -pffserial
+addPromDevice -p 1 -name xcf04s
+addDesign -version 0 -name 0
+addDeviceChain -index 0
+addDevice -p 1 -file generated/core_top.bit
+generate -format mcs -fillvalue FF -output generated/core_top.mcs
+quit
--- /dev/null
+SHELL := bash
+
+VHDL_DIR := ../cpu/src
+PROJ_VHDL = \
+ core_top_s3e.vhd \
+ alu_b.vhd \
+ alu_pkg.vhd \
+ alu.vhd \
+ common_pkg.vhd \
+ core_pkg.vhd \
+ decoder_b.vhd \
+ decoder.vhd \
+ decode_stage_b.vhd \
+ decode_stage.vhd \
+ exec_op/add_op_b.vhd \
+ exec_op/and_op_b.vhd \
+ exec_op/or_op_b.vhd \
+ exec_op/shift_op_b.vhd \
+ exec_op/xor_op_b.vhd \
+ exec_op.vhd \
+ execute_stage_b.vhd \
+ execute_stage.vhd \
+ extension_b.vhd \
+ extension_interrupt_b.vhd \
+ extension_interrupt.vhd \
+ extension_pkg.vhd \
+ extension_uart_b.vhd \
+ extension_uart_pkg.vhd \
+ extension_uart.vhd \
+ extension_7seg_b.vhd \
+ extension_7seg_pkg.vhd \
+ extension_7seg.vhd \
+ extension_imp_b.vhd \
+ extension_imp_pkg.vhd \
+ extension_imp.vhd \
+ extension.vhd \
+ fetch_stage_b.vhd \
+ fetch_stage.vhd \
+ mem_pkg.vhd \
+ r2_w_ram_b.vhd \
+ r2_w_ram.vhd \
+ rom_b.vhd \
+ rom.vhd \
+ rs232_rx_arc.vhd \
+ rs232_rx.vhd \
+ rs232_tx_arc.vhd \
+ rs232_tx.vhd \
+ ram_xilinx.vhd \
+ ram_xilinx_b.vhd \
+ r_w_ram_b.vhd \
+ r_w_ram.vhd \
+ rw_r_ram_b.vhd \
+ rw_r_ram.vhd \
+ writeback_stage_b.vhd \
+ writeback_stage.vhd
+
+PROJ_VHDL := $(foreach n,$(PROJ_VHDL),$(VHDL_DIR)/$(n))
+
+NAME := core_top
+
+
+all: generated/$(NAME).mcs
+
+generated:
+ rm -rf generated
+ mkdir generated
+
+clean:
+ rm -rf *.o *.cf tb *.vcd $(NAME) $(SIM_TOP) *.ghw
+ rm -f *.bit *.bgn *_pad.txt *_pad.csv *.xpi *.srp *.ngc *.par
+ rm -f *.lst *.ngd *.ngm *.pcf *.mrp *.unroutes *.pad
+ rm -f *.bld *.ncd *.twr *.drc
+ rm -f *.map *.xrpt *.log *.twx *.xml *.ptwx
+ rm -rf xst $(NAME).prj
+ rm -rf generated/
+ rm -rf xlnx_auto_0_xdb _xmsgs
+
+#Xilinx ISE actions. Uses a wrapper script named "xilinx" to run the ISE batch commands
+
+# create an ISE project file from the list of VHDL files
+$(NAME).prj: $(PROJ_VHDL)
+ echo $(PROJ_VHDL) |tr " " "\n">$(NAME).prj
+
+bitfile: generated step0 step1 step2 step3 step4 step5
+
+step0: $(NAME).prj
+ xst -ifn ISE_scripts/$(NAME).scrs -ofn $(NAME).srp
+step1:
+ ngdbuild -nt on -uc spartan3e.ucf $(NAME).ngc $(NAME).ngd
+step2:
+ map -pr b $(NAME).ngd -o $(NAME).ncd $(NAME).pcf
+step3:
+ par -w -ol high $(NAME).ncd $(NAME).ncd $(NAME).pcf
+step4:
+ trce -v 10 -o $(NAME).twr $(NAME).ncd $(NAME).pcf
+step5:
+ bitgen $(NAME).ncd generated/$(NAME).bit -w #-f $(NAME).ut
+
+generated/$(NAME).bit: bitfile
+
+jtag: generated/$(NAME).bit
+ impact -batch ISE_scripts/loadjtag.cmds
+
+mcs: generated/$(NAME).bit
+ impact -batch ISE_scripts/makeprom.cmds
+
+generated/$(NAME).mcs: mcs
+
+load: generated/$(NAME).mcs
+ impact -batch ISE_scripts/loadprom.cmds
+
+impact:
+ impact
+
+ise: $(NAME).prj
+ ise
--- /dev/null
+#####################################################
+### SPARTAN-3E STARTER KIT BOARD CONSTRAINTS FILE
+#####################################################
+# ==== Analog-to-Digital Converter (ADC) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "AD_CONV" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+# ==== Programmable Gain Amplifier (AMP) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "AMP_CS" LOC = "N7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "AMP_DOUT" LOC = "E18" | IOSTANDARD = LVCMOS33 ;
+#NET "AMP_SHDN" LOC = "P7" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+# ==== Pushbuttons (BTN) ====
+#NET "BTN_EAST" LOC = "H13" | IOSTANDARD = LVTTL | PULLDOWN ;
+#NET "BTN_NORTH" LOC = "V4" | IOSTANDARD = LVTTL | PULLDOWN ;
+NET "sys_res" LOC = "K17" | IOSTANDARD = LVTTL | PULLDOWN ;
+#NET "btn_a" LOC = "D18" | IOSTANDARD = LVTTL | PULLDOWN ;
+# ==== Clock inputs (CLK) ====
+NET "sys_clk" LOC = "C9" | IOSTANDARD = LVCMOS33 ;
+# Define clock period for 50 MHz oscillator (40%/60% duty-cycle)
+NET "sys_clk" PERIOD = 20 ns HIGH 40 % ;
+#NET "CLK_AUX" LOC = "B8" | IOSTANDARD = LVCMOS33 ;
+#NET "CLK_SMA" LOC = "A10" | IOSTANDARD = LVCMOS33 ;
+# ==== Digital-to-Analog Converter (DAC) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "DAC_CLR" LOC = "P8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "DAC_CS" LOC = "N8" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+# ==== 1-Wire Secure EEPROM (DS)
+#NET "DS_WIRE" LOC = "U4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+# ==== Ethernet PHY (E) ====
+#NET "E_COL" LOC = "U6" | IOSTANDARD = LVCMOS33 ;
+#NET "E_CRS" LOC = "U13" | IOSTANDARD = LVCMOS33 ;
+#NET "E_MDC" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_MDIO" LOC = "U5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_RX_CLK" LOC = "V3" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RX_DV" LOC = "V2" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<0>" LOC = "V8" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<1>" LOC = "T11" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<2>" LOC = "U11" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<3>" LOC = "V14" | IOSTANDARD = LVCMOS33 ;
+#NET "E_RXD<4>" LOC = "U14" | IOSTANDARD = LVCMOS33 ;
+#NET "E_TX_CLK" LOC = "T7" | IOSTANDARD = LVCMOS33 ;
+#NET "E_TX_EN" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<0>" LOC = "R11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<1>" LOC = "T15" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<2>" LOC = "R5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<3>" LOC = "T5" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "E_TXD<4>" LOC = "R6" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+# ==== FPGA Configuration Mode, INIT_B Pins (FPGA) ====
+#NET "FPGA_M0" LOC = "M10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "FPGA_M1" LOC = "V11" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "FPGA_M2" LOC = "T10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
+#NET "FPGA_INIT_B" LOC = "T3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+#NET "FPGA_RDWR_B" LOC = "U10" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 ;
+#NET "FPGA_HSWAP" LOC = "B3" | IOSTANDARD = LVCMOS33 ;
+# ==== FX2 Connector (FX2) ====
+#NET "FX2_CLKIN" LOC = "E10" | IOSTANDARD = LVCMOS33 ;
+#NET "FX2_CLKIO" LOC = "D9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_CLKOUT" LOC = "D10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# These four connections are shared with the J1 6-pin accessory header
+#NET "FX2_IO<1>" LOC = "B4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<2>" LOC = "A4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<3>" LOC = "D5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<4>" LOC = "C5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# These four connections are shared with the J2 6-pin accessory header
+#NET "FX2_IO<5>" LOC = "A6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<6>" LOC = "B6" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<7>" LOC = "E7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<8>" LOC = "F7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# These four connections are shared with the J4 6-pin accessory header
+#NET "FX2_IO<9>" LOC = "D7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<10>" LOC = "C7" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<11>" LOC = "F8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<12>" LOC = "E8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# The discrete LEDs are shared with the following 8 FX2 connections
+#NET "FX2_IO<13>" LOC = "F9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<14>" LOC = "E9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<15>" LOC = "D11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<16>" LOC = "C11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<17>" LOC = "F11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<18>" LOC = "E11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<19>" LOC = "E12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<20>" LOC = "F12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<21>" LOC = "A13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<22>" LOC = "B13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<23>" LOC = "A14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<24>" LOC = "B14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<25>" LOC = "C14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<26>" LOC = "D14" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<27>" LOC = "A16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<28>" LOC = "B16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<29>" LOC = "E13" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<30>" LOC = "C4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<31>" LOC = "B11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<32>" LOC = "A11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<33>" LOC = "A8" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<34>" LOC = "G9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<35>" LOC = "D12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<36>" LOC = "C12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<37>" LOC = "A15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<38>" LOC = "B15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IO<39>" LOC = "C3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+#NET "FX2_IP<40>" LOC = "C15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ;
+# ==== 6-pin header J1 ====
+# These are shared connections with the FX2 connector
+#NET "J1<0>" LOC = "B4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<1>" LOC = "A4" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<2>" LOC = "D5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J1<3>" LOC = "C5" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+# ==== 6-pin header J2 ====
+# These are shared connections with the FX2 connector
+#NET "J2<0>" LOC = "A6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<1>" LOC = "B6" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<2>" LOC = "E7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J2<3>" LOC = "F7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+# ==== 6-pin header J4 ====
+# These are shared connections with the FX2 connector
+#NET "J4<0>" LOC = "D7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<1>" LOC = "C7" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<2>" LOC = "F8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+#NET "J4<3>" LOC = "E8" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 6 ;
+# ==== Character LCD (LCD) ====
+#NET "LCD_E" LOC = "M18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "LCD_RS" LOC = "L18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "LCD_RW" LOC = "L17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+# LCD data connections are shared with StrataFlash connections SF_D<11:8>
+#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+# ==== Discrete LEDs (LED) ====
+# These are shared connections with the FX2 connector
+#NET "LED0" LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED1" LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<2>" LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<3>" LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<4>" LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<5>" LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<6>" LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+#NET "LED<7>" LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8 ;
+# ==== PS/2 Mouse/Keyboard Port (PS2) ====
+#NET "PS2_CLK" LOC = "G14" | IOSTANDARD = LVCMOS33 ;
+#NET "PS2_DATA" LOC = "G13" | IOSTANDARD = LVCMOS33 ;
+# ==== Rotary Pushbutton Switch (ROT) ====
+#NET "ROT_A" LOC = "K18" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "ROT_B" LOC = "G18" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "ROT_CENTER" LOC = "V16" | IOSTANDARD = LVTTL | PULLDOWN ;
+# ==== RS-232 Serial Ports (RS232) ====
+NET "bus_rx" LOC = "E8" | IOSTANDARD = LVTTL ;
+NET "bus_tx" LOC = "F8" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
+#NET "RS232_DTE_RXD" LOC = "U8" | IOSTANDARD = LVTTL ;
+#NET "RS232_DTE_TXD" LOC = "M13" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = SLOW ;
+# ==== DDR SDRAM (SD) ==== (I/O Bank 3, VCCO=2.5V)
+#NET "SD_A<0>" LOC = "T1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<1>" LOC = "R3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<2>" LOC = "R2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<3>" LOC = "P1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<4>" LOC = "F4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<5>" LOC = "H4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<6>" LOC = "H3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<7>" LOC = "H1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<8>" LOC = "H2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<9>" LOC = "N4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<10>" LOC = "T2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<11>" LOC = "N5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_A<12>" LOC = "P2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_BA<0>" LOC = "K5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_BA<1>" LOC = "K6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CAS" LOC = "C2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CK_N" LOC = "J4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CK_P" LOC = "J5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CKE" LOC = "K3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_CS" LOC = "K4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<0>" LOC = "L2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<1>" LOC = "L1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<2>" LOC = "L3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<3>" LOC = "L4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<4>" LOC = "M3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<5>" LOC = "M4" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<6>" LOC = "M5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<7>" LOC = "M6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<8>" LOC = "E2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<9>" LOC = "E1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<10>" LOC = "F1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<11>" LOC = "F2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<12>" LOC = "G6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<13>" LOC = "G5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<14>" LOC = "H6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_DQ<15>" LOC = "H5" | IOSTANDARD = SSTL2_I ;
+#NET "SD_LDM" LOC = "J2" | IOSTANDARD = SSTL2_I ;
+#NET "SD_LDQS" LOC = "L6" | IOSTANDARD = SSTL2_I ;
+#NET "SD_RAS" LOC = "C1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_UDM" LOC = "J1" | IOSTANDARD = SSTL2_I ;
+#NET "SD_UDQS" LOC = "G3" | IOSTANDARD = SSTL2_I ;
+#NET "SD_WE" LOC = "D1" | IOSTANDARD = SSTL2_I ;
+# Path to allow connection to top DCM connection
+#NET "SD_CK_FB" LOC = "B9" | IOSTANDARD = LVCMOS33 ;
+# Prohibit VREF pins
+CONFIG PROHIBIT = D2;
+CONFIG PROHIBIT = G4;
+CONFIG PROHIBIT = J6;
+CONFIG PROHIBIT = L5;
+CONFIG PROHIBIT = R4;
+# ==== Intel StrataFlash Parallel NOR Flash (SF) ====
+#NET "SF_A<0>" LOC = "H17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<2>" LOC = "J12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<3>" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<4>" LOC = "J15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<5>" LOC = "J16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<6>" LOC = "J17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<7>" LOC = "K14" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<8>" LOC = "K15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<9>" LOC = "K12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<10>" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<11>" LOC = "L15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<12>" LOC = "L16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<13>" LOC = "T18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<14>" LOC = "R18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<15>" LOC = "T17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<16>" LOC = "U18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<17>" LOC = "T16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<18>" LOC = "U15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<19>" LOC = "V15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<20>" LOC = "T12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<21>" LOC = "V13" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<22>" LOC = "V12" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<23>" LOC = "N11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_A<24>" LOC = "A11" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_BYTE" LOC = "C17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_CE0" LOC = "D16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<1>" LOC = "P10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<2>" LOC = "R10" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<3>" LOC = "V9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<4>" LOC = "U9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<5>" LOC = "R9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<6>" LOC = "M9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<7>" LOC = "N9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<8>" LOC = "R15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<9>" LOC = "R16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<10>" LOC = "P17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<11>" LOC = "M15" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<12>" LOC = "M16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<13>" LOC = "P6" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<14>" LOC = "R8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_D<15>" LOC = "T8" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_OE" LOC = "C18" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "SF_STS" LOC = "B18" | IOSTANDARD = LVCMOS33 ;
+#NET "SF_WE" LOC = "D17" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+# ==== STMicro SPI serial Flash (SPI) ====
+# some connections shared with SPI Flash, DAC, ADC, and AMP
+#NET "SPI_MISO" LOC = "N10" | IOSTANDARD = LVCMOS33 ;
+#NET "SPI_MOSI" LOC = "T4" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "SPI_SCK" LOC = "U16" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "SPI_SS_B" LOC = "U3" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+#NET "SPI_ALT_CS_JP11" LOC = "R12" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 6 ;
+# ==== Slide Switches (SW) ====
+#NET "SW<0>" LOC = "L13" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "SW<1>" LOC = "L14" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "SW<2>" LOC = "H18" | IOSTANDARD = LVTTL | PULLUP ;
+#NET "SW<3>" LOC = "N17" | IOSTANDARD = LVTTL | PULLUP ;
+# ==== VGA Port (VGA) ====
+#NET "b<0>" LOC = "G15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+#NET "g<0>" LOC = "H15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+#NET "hsync_n" LOC = "F15" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+#NET "r<0>" LOC = "H14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+#NET "vsync_n" LOC = "F14" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+# ==== Xilinx CPLD (XC) ====
+#NET "XC_CMD<0>" LOC = "P18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_CMD<1>" LOC = "N18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_CPLD_EN" LOC = "B10" | IOSTANDARD = LVTTL ;
+#NET "XC_D<0>" LOC = "G16" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_D<1>" LOC = "F18" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_D<2>" LOC = "F17" | IOSTANDARD = LVTTL | DRIVE = 4 | SLEW = SLOW ;
+#NET "XC_TRIG" LOC = "R17" | IOSTANDARD = LVCMOS33 ;
+#NET "XC_GCK0" LOC = "H16" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+#NET "GCLK10" LOC = "C9" | IOSTANDARD = LVCMOS33 | DRIVE = 4 | SLEW = SLOW ;
+NET "sys_clk" TNM_NET = "sys_clk";
+#NET "clk_reg1" TNM_NET = "clk_reg1";
+#TIMESPEC "TS_clk_reg1" = PERIOD "clk_reg1" 40 ns HIGH 50 %;
projects / calu.git / commitdiff