--right_o <= displacement;
addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));
if op_detail(IMM_OPT) = '1' then
- result_v.result := right_operand;
+
+ result_v.result := right_operand;
+
+ if (op_detail(LDI_REPLACE_OPT) = '0') then
+ result_v.result := left_operand;
+ if (op_detail(LOW_HIGH_OPT) = '1') then
+ result_v.result(31 downto 16) := right_operand(31 downto 16);
+ else
+ result_v.result(15 downto 0) := right_operand(15 downto 0);
+ end if;
+ end if;
+
res_prod := '1';
mem_op := '0';
addr(DATA_ADDR_WIDTH + 2) <= '0';
constant ARITH_OPT : integer := 1;
constant HWORD_OPT : integer := 1;
constant PUSH_OPT : integer := 1;
+ constant LOW_HIGH_OPT : integer := 1;
constant CARRY_OPT : integer := 2;
constant BYTE_OPT : integer := 2;
+ constant LDI_REPLACE_OPT : integer := 2;
constant RIGHT_OPT : integer := 3;
constant JMP_REG_OPT : integer := 3;
port(
--System input pins
- sys_res : in std_logic;
+ sys_res_unsync : in std_logic;
sys_clk : in std_logic;
-- result : out gp_register_t;
-- reg_wr_data : out gp_register_t
architecture behav of core_top is
+ constant SYNC_STAGES : integer := 2;
+ constant RESET_VALUE : std_logic := '0';
+
signal jump_result : instruction_addr_t;
signal jump_result_pin : instruction_addr_t;
signal prediction_result_pin : instruction_addr_t;
signal gpm_in_pin : extmod_rec;
signal gpm_out_pin : gp_register_t;
signal nop_pin : std_logic;
+
+ signal sys_res : std_logic;
signal vers, vers_nxt : exec2wb_rec;
+ signal sync : std_logic_vector(1 to SYNC_STAGES);
begin
fetch_st : fetch_stage
vers.dmem_write_en <= '0';
vers.hword <= '0';
vers.byte_s <= '0';
+ sync <= (others => '0');
elsif rising_edge(sys_clk) then
vers <= vers_nxt;
+
+ sync(1) <= sys_res_unsync xor RESET_VALUE;
+ for i in 2 to SYNC_STAGES loop
+ sync(i) <= sync(i - 1);
+ end loop;
+
end if;
end process;
+sys_res <= sync(SYNC_STAGES);
--init : process(all)
end if;
if (instr_s.opcode = "11010") then --ldi
+ instr_s.reg_src1_addr := instr_s.reg_dest_addr;
+ instr_s.op_detail(LOW_HIGH_OPT) := instr_s.high_low;
+ instr_s.op_detail(LDI_REPLACE_OPT) := instr_s.signext;
+
if (instr_s.high_low = '1') then
instr_s.immediate(31 downto 16) := instruction(18 downto 3);
instr_s.immediate(15 downto 0) := (others => '0');
else
instr_s.immediate(15 downto 0) := instruction(18 downto 3);
instr_s.immediate(31 downto 16) := (others => '0');
-
- --instr_s.immediate(11 downto 0) := instruction(14 downto 3);
- --instr_s.immediate(WORD_WIDTH-1 downto 12) := (others => '0');
end if;
if (instr_s.signext = '1' and instr_s.immediate(11) = '1') then
begin
- instruction_ram : r_w_ram --rom
+ instruction_ram : rom --r_w_ram --rom
generic map (
PHYS_INSTR_ADDR_WIDTH,
WORD_WIDTH
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
-set_location_assignment PIN_42 -to sys_res
-set_location_assignment PIN_166 -to bus_tx
+set_location_assignment PIN_178 -to bus_tx
set_location_assignment PIN_152 -to sys_clk
set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "AS INPUT TRI-STATED"
set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
set_global_assignment -name MUX_RESTRUCTURE OFF
set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_location_assignment PIN_153 -to bus_rx
+set_location_assignment PIN_42 -to sys_res_unsync
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file