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dt_inc/deepjit: deepjit uses dt_inc
authorMartin Perner <martin@perner.cc>
Fri, 14 Jan 2011 13:15:14 +0000 (14:15 +0100)
committerMartin Perner <martin@perner.cc>
Fri, 14 Jan 2011 13:15:14 +0000 (14:15 +0100)
progs/deepjit.s patch | blob | history
progs/dt_inc.s patch | blob | history

diff --git a/progs/deepjit.s b/progs/deepjit.s
index 1436b63c6048139336aca09894acb6415eeb58d8..871879aed2da7e32eaa8a5c86586a324a33808ed 100644 (file)
--- a/progs/deepjit.s
+++ b/progs/deepjit.s
@@ -1,4 +1,5 @@
 #define PROGINSTR stw r0, PDATA(r13)
 #define PROGINSTR stw r0, PDATA(r13)
+#include "dt_inc.s"
 .data
 .org 0x10
 inputdata:
 .data
 .org 0x10
 inputdata:
@@ -103,49 +104,25 @@ prog_not:
 .ifill push r6
 
 .text
 .ifill push r6
 
 .text
-       .define UART_BASE, 0x2000
-       .define UART_STATUS, 0x0
-       .define UART_RECV, 0xc
-       .define UART_TRANS, 0x8
-
-       .define UART_TRANS_EMPTY, 0x1
-       .define UART_RECV_NEW, 0x2
-
-       .define PBASE, 0x2030
-       .define PADDR, 0x4
-       .define PDATA, 0x8
 .org 0
 start:
 .org 0
 start:
-       call main
-       call main
+       call+ main
+       call+ main
        ret
 
 
 main:
 
        ret
 
 
 main:
 
-       ldi  r10, UART_BASE@lo
-       ldih r10, UART_BASE@hi
-;recv byte
-u_recv_byte:
-       ldw r3, UART_STATUS(r10)
-       andx r3, UART_RECV_NEW
-       brzs+ u_recv_byte; branch if zero
-
-       ldw r0, UART_RECV(r10)
-;recv byte
-       ldis r0, 0x48
-u_test:
-       ldw r9, UART_STATUS(r10)
-       andx r9, UART_TRANS_EMPTY
-       brnz+ u_test ; branch if not zero
-       stb r0, UART_TRANS(r10)
+       call+ u_init
+       call+ u_recv_byte
 
 
+       ldis r1, 0x48
+       call+ u_send_byte
 
        ;set address of input
        ldis r1, inputdata@lo
        ldih r1, inputdata@hi
 
 
        ;set address of input
        ldis r1, inputdata@lo
        ldih r1, inputdata@hi
 
-
        ;set address of program start
        ldis r2, (prog_start/4)@lo
        ldih r2, (prog_start/4)@hi
        ;set address of program start
        ldis r2, (prog_start/4)@lo
        ldih r2, (prog_start/4)@hi
@@ -161,7 +138,6 @@ u_test:
        ldis r13, PBASE@lo
        ldih r13, PBASE@hi
 
        ldis r13, PBASE@lo
        ldih r13, PBASE@hi
 
-
        ;set programmer address
        stw r2, PADDR(r13)
 
        ;set programmer address
        stw r2, PADDR(r13)
 
@@ -180,26 +156,10 @@ u_test:
        ;call jit'ed prog
        call+ prog_start
 
        ;call jit'ed prog
        call+ prog_start
 
-;send result
-       push r0
-       ldi  r10, UART_BASE@lo
-       ldih r10, UART_BASE@hi
-
-u_send_byte1:
-       ldw r9, UART_STATUS(r10)
-       andx r9, UART_TRANS_EMPTY
-       brnz+ u_send_byte1 ; branch if not zero
-       ldis r0, 0x50
-       stb r0, UART_TRANS(r10)
-
-u_send_byte:
-       ldw r9, UART_STATUS(r10)
-       andx r9, UART_TRANS_EMPTY
-       brnz+ u_send_byte ; branch if not zero
-       pop r0
-       stb r0, UART_TRANS(r10)
-
-;send result
+       call+ u_init
+
+       mov r1, r0
+       call+ u_send_byte
 
        br+ main
 
 
        br+ main
 
diff --git a/progs/dt_inc.s b/progs/dt_inc.s
index ad347c129d180751828f15c049e3e1ae713c82b3..50165b9a7054e944fca1c4d1dbd02ee7202df1df 100644 (file)
--- a/progs/dt_inc.s
+++ b/progs/dt_inc.s
@@ -1,7 +1,6 @@
 .data
 
 .data
 
-; TODO
-.org 0x300
+.org 0xA00
 int2hex:
        ;3210
        .fill 0x33323130 
 int2hex:
        ;3210
        .fill 0x33323130 
@@ -12,8 +11,7 @@ int2hex:
        ;fedc
        .fill 0x66656463
 .text
        ;fedc
        .fill 0x66656463
 .text
-; TODO
-.org 0x300
+.org 0x400
        .define UART_BASE, 0x2000
        .define UART_STATUS, 0x0
        .define UART_RECV, 0xc
        .define UART_BASE, 0x2000
        .define UART_STATUS, 0x0
        .define UART_RECV, 0xc
@@ -22,6 +20,10 @@ int2hex:
        .define UART_TRANS_EMPTY, 0x1
        .define UART_RECV_NEW, 0x2
 
        .define UART_TRANS_EMPTY, 0x1
        .define UART_RECV_NEW, 0x2
 
+       .define PBASE, 0x2030
+       .define PADDR, 0x4
+       .define PDATA, 0x8
+
        .define SSEG_BASE, 0x2010
 
        .define INT_BASE, 0x2020
        .define SSEG_BASE, 0x2010
 
        .define INT_BASE, 0x2020
@@ -30,28 +32,21 @@ int2hex:
        .define INT_UART_REC_BIT, 0x02
 
 u_recv_byte:
        .define INT_UART_REC_BIT, 0x02
 
 u_recv_byte:
-#ifndef DTSIM
        ldw r3, UART_STATUS(r10)
        andx r3, UART_RECV_NEW
        brzs+ u_recv_byte; branch if zero
        xor r0, r0, r0
        ldw r0, UART_RECV(r10)
        ldw r3, UART_STATUS(r10)
        andx r3, UART_RECV_NEW
        brzs+ u_recv_byte; branch if zero
        xor r0, r0, r0
        ldw r0, UART_RECV(r10)
-#else
-       ldis r0, 0x41 ; 'A'
-#endif
        ret
 
 u_send_byte:
        ret
 
 u_send_byte:
-#ifndef DTSIM
        ldw r9, UART_STATUS(r10)
        andx r9, UART_TRANS_EMPTY
        brnz+ u_send_byte ; branch if not zero
        stb r1, UART_TRANS(r10)
        ldw r9, UART_STATUS(r10)
        andx r9, UART_TRANS_EMPTY
        brnz+ u_send_byte ; branch if not zero
        stb r1, UART_TRANS(r10)
-#endif
        ret
 
 u_send_uint:
        ret
 
 u_send_uint:
-#ifndef DTSIM
        addi r8, r1, 0
        ;usb_sendbuffersafe ("0x", 2);
        xor r1, r1, r1
        addi r8, r1, 0
        ;usb_sendbuffersafe ("0x", 2);
        xor r1, r1, r1
@@ -79,12 +74,8 @@ u_send_uint_loop:
        lls r8, r8, 4
        addi r7, r7, 1
        br u_send_uint_loop
        lls r8, r8, 4
        addi r7, r7, 1
        br u_send_uint_loop
-#else
-       ret
-#endif
 
 u_send_string:
 
 u_send_string:
-#ifndef DTSIM
        ; r1 = addr
        ; r2 = len
        addi r3, r1, 0
        ; r1 = addr
        ; r2 = len
        addi r3, r1, 0
@@ -96,31 +87,22 @@ u_send_string_int:
        addis r2, r2, 0-1
        addi r3, r3, 1
        br u_send_string_int
        addis r2, r2, 0-1
        addi r3, r3, 1
        br u_send_string_int
-#else
-       ret
-#endif
 
 u_send_newline:
 
 u_send_newline:
-#ifndef DTSIM
        xor r1, r1, r1
        ldi r1, 0x0a
        call u_send_byte
        ldi r1, 0x0d
        call u_send_byte
        xor r1, r1, r1
        ldi r1, 0x0a
        call u_send_byte
        ldi r1, 0x0d
        call u_send_byte
-#endif
        ret
 
 u_init:
        ret
 
 u_init:
-#ifndef DTSIM
        xor r10, r10, r10
        ldi r10, UART_BASE@lo
        ldih r10, UART_BASE@hi
        xor r10, r10, r10
        ldi r10, UART_BASE@lo
        ldih r10, UART_BASE@hi
-#endif
        ret
 
 sseg_displ:
        ret
 
 sseg_displ:
-#ifndef DTSIM
        ldi r2, SSEG_BASE
        stw r1, 0(r2)
        ldi r2, SSEG_BASE
        stw r1, 0(r2)
-#endif
        ret
        ret
Deep Thought (softcore CPU)