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static branch - getestet, 58MHz lt quartus
author
Stefan Rebernig
<stefan.rebernig@gmail.com>
Wed, 1 Dec 2010 22:23:56 +0000
(23:23 +0100)
committer
Stefan Rebernig
<stefan.rebernig@gmail.com>
Wed, 1 Dec 2010 22:23:56 +0000
(23:23 +0100)
cpu/create_project.tcl
patch
|
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|
history
cpu/src/core_top.vhd
patch
|
blob
|
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cpu/src/decode_stage_b.vhd
patch
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cpu/src/r_w_ram_b.vhd
patch
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cpu/src/writeback_stage_b.vhd
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diff --git
a/cpu/create_project.tcl
b/cpu/create_project.tcl
index 0b13c22d8fcf19cf3a00c3f3942085be229ae6cf..53644154cfe5a8c2f10a494e538d70f3e34c3835 100755
(executable)
--- a/
cpu/create_project.tcl
+++ b/
cpu/create_project.tcl
@@
-51,6
+51,9
@@
if {$make_assignments} {
set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
set_global_assignment -name VHDL_FILE ../src/gpm_pkg.vhd
set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
set_global_assignment -name VHDL_FILE ../src/gpm_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_pkg.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension.vhd
+ set_global_assignment -name VHDL_FILE ../src/extension_b.vhd
set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
set_global_assignment -name VHDL_FILE ../src/exec_op.vhd
set_global_assignment -name VHDL_FILE ../src/exec_op/add_op_b.vhd
@@
-62,8
+65,8
@@
if {$make_assignments} {
set_global_assignment -name VHDL_FILE ../src/alu.vhd
set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
set_global_assignment -name VHDL_FILE ../src/alu.vhd
set_global_assignment -name VHDL_FILE ../src/alu_b.vhd
-
set_global_assignment -name VHDL_FILE ../src/gpm.vhd
-
set_global_assignment -name VHDL_FILE ../src/gpm_b.vhd
+
#
set_global_assignment -name VHDL_FILE ../src/gpm.vhd
+
#
set_global_assignment -name VHDL_FILE ../src/gpm_b.vhd
set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
set_global_assignment -name VHDL_FILE ../src/execute_stage.vhd
set_global_assignment -name VHDL_FILE ../src/execute_stage_b.vhd
diff --git
a/cpu/src/core_top.vhd
b/cpu/src/core_top.vhd
index f0e1a4ac069af9971e4b8ece779b6571ca698170..bb9578936f77f1307fb83f91b983ddbaf144c095 100644
(file)
--- a/
cpu/src/core_top.vhd
+++ b/
cpu/src/core_top.vhd
@@
-26,6
+26,7
@@
architecture behav of core_top is
signal branch_prediction_bit_pin : std_logic;
signal alu_jump_bit_pin : std_logic;
signal instruction_pin : instruction_word_t;
signal branch_prediction_bit_pin : std_logic;
signal alu_jump_bit_pin : std_logic;
signal instruction_pin : instruction_word_t;
+ signal prog_cnt_pin : instruction_addr_t;
signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
signal reg_wr_data_pin : gp_register_t;
signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
signal reg_wr_data_pin : gp_register_t;
@@
-71,7
+72,8
@@
begin
alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
--Data outputs
alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
--Data outputs
- instruction => instruction_pin --: out instruction_word_t
+ instruction => instruction_pin, --: out instruction_word_t
+ prog_cnt => prog_cnt_pin
);
decode_st : decode_stage
);
decode_st : decode_stage
@@
-89,6
+91,7
@@
begin
--Data inputs
instruction => instruction_pin, --: in instruction_word_t;
--Data inputs
instruction => instruction_pin, --: in instruction_word_t;
+ prog_cnt => prog_cnt_pin,
reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
reg_we => reg_we_pin, --: in std_logic;
reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
reg_we => reg_we_pin, --: in std_logic;
@@
-127,7
+130,7
@@
begin
--end process;
result <= result_pin;
--end process;
result <= result_pin;
- nop_pin <= (alu_jump_bit_pin xor brpr_pin);
+ nop_pin <= (alu_jump_bit_pin
); --
xor brpr_pin);
jump_result <= jump_result_pin;
jump_result <= jump_result_pin;
diff --git
a/cpu/src/decode_stage_b.vhd
b/cpu/src/decode_stage_b.vhd
index dc5e389b7527bf11aad11cbd5580728b0a08669a..60cc287c509d231900a6aaad0ccaa16a4e3f9d6a 100644
(file)
--- a/
cpu/src/decode_stage_b.vhd
+++ b/
cpu/src/decode_stage_b.vhd
@@
-109,7
+109,7
@@
end process;
-- fills output register
-- fills output register
-to_next: process(instr_spl)
+to_next: process(instr_spl
, prog_cnt
)
begin
dec_op_inst_nxt.condition <= instr_spl.predicates;
begin
dec_op_inst_nxt.condition <= instr_spl.predicates;
@@
-180,7
+180,7
@@
end process;
-- async process: calculates branch prediction
-- async process: calculates branch prediction
-br_pred: process(instr_spl)
+br_pred: process(instr_spl
, prog_cnt
)
begin
begin
diff --git
a/cpu/src/r_w_ram_b.vhd
b/cpu/src/r_w_ram_b.vhd
index 585dc9260adcc46f276ef62ee4626ba43342fc6f..023b1b7fa27ffd6a0918798cbe964e0c48813466 100644
(file)
--- a/
cpu/src/r_w_ram_b.vhd
+++ b/
cpu/src/r_w_ram_b.vhd
@@
-12,7
+12,8
@@
architecture behaviour of r_w_ram is
-- r0 = 0, r1 = 1, r2 = 3, r3 = A
-- r0 = 0, r1 = 1, r2 = 3, r3 = A
- signal ram : RAM_TYPE := (
+ signal ram : RAM_TYPE := ( 0 => "11101101000000000000000000000000", -- r0 = 0
+
1 => "11101101000010000000000000111000", -- r1 = 7
2 => "11101101000100000000000000101000", -- r2 = 5
3 => "11101101000110000000000000100000", -- r3 = 4
1 => "11101101000010000000000000111000", -- r1 = 7
2 => "11101101000100000000000000101000", -- r2 = 5
3 => "11101101000110000000000000100000", -- r3 = 4
@@
-20,15
+21,17
@@
architecture behaviour of r_w_ram is
5 => "11100010001010100000100000000000", -- r5 = r4 and r1
6 => "11100001000000000000000000001000", -- r0 = r0 + 1
5 => "11100010001010100000100000000000", -- r5 = r4 and r1
6 => "11100001000000000000000000001000", -- r0 = r0 + 1
- 7 => "1110110010000000000000000001
0000", -- cmpi r0 , 2 => 2-2 => 1001
+ 7 => "1110110010000000000000000001
1000", -- cmpi r0 , 2
8 => "00001011011111111111110010000011", -- jump -7
9 => "11101011000000000000000010000010", -- jump +1
10 => "11100111101010100000000000000001", -- stw r5,r4,1
8 => "00001011011111111111110010000011", -- jump -7
9 => "11101011000000000000000010000010", -- jump +1
10 => "11100111101010100000000000000001", -- stw r5,r4,1
- 11 => "11101100001000100000000000000000", --cmp r4 , r4 => 2-2 => 1001
+ 11 => "11101100001000100000000000000000", -- cmp r4 , r4 => 2-2 => 1001
+
+ 12 => "11101011000000000000000000000010", -- jump +0
- 0 => "11101101000000000000000000000000", -- r0 = 0
+
others => x"F0000000");
others => x"F0000000");
diff --git
a/cpu/src/writeback_stage_b.vhd
b/cpu/src/writeback_stage_b.vhd
index 357368003f4202e20e0d483e0107ed0a9d772331..862c1d35d5bb9c6bec8542afa8c8dde18c444901 100644
(file)
--- a/
cpu/src/writeback_stage_b.vhd
+++ b/
cpu/src/writeback_stage_b.vhd
@@
-95,11
+95,12
@@
begin
end if;
end if;
end if;
end if;
- jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
+ --jump <= (alu_jmp xor br_pred) and (write_en or wb_reg.dmem_en);
+ jump <= (alu_jmp xor br_pred);-- and (write_en or wb_reg.dmem_en);
-
if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
-
jump <= '1';
-
end if;
+
--
if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
+
--
jump <= '1';
+
--
end if;
jump_addr <= result;
if ((alu_jmp and wb_reg.dmem_en) = '1') then
jump_addr <= result;
if ((alu_jmp and wb_reg.dmem_en) = '1') then
@@
-128,7
+129,7
@@
begin
end process;
end process;
-addr_de_mult: process(wb_reg_nxt.address)
+addr_de_mult: process(wb_reg_nxt.address
, ram_data, wb_reg
)
begin
begin