uart:uart entitiy

diff --git a/cpu/sim/testcore1.do b/cpu/sim/testcore1.do
index def1de97dd2015ea9cb9843d8a044cefc49b820a..0126674588c2087802611f0d8b65020a0400d4da 100644 (file)
--- a/cpu/sim/testcore1.do
+++ b/cpu/sim/testcore1.do
@@ -17,7 +17,7 @@ vcom -work work ../src/decode_stage_b.vhd
 
 vcom -work work ../src/alu_pkg.vhd
 vcom -work work ../src/extension_pkg.vhd
-vcom -work work ../src/gpm_pkg.vhd
+
 
 vcom -work work ../src/exec_op.vhd
 vcom -work work ../src/exec_op/add_op_b.vhd
@@ -36,6 +36,13 @@ vcom -work work ../src/extension_pkg.vhd
 vcom -work work ../src/extension.vhd
 vcom -work work ../src/extension_b.vhd
 
+
+vcom -work work ../src/extension_uart_pkg.vhd
+vcom -work work ../src/rs232_tx.vhd
+vcom -work work ../src/rs232_tx_arc.vhd
+vcom -work work ../src/extension_uart.vhd
+vcom -work work ../src/extension_uart_b.vhd
+
 vcom -work work ../src/execute_stage.vhd
 vcom -work work ../src/execute_stage_b.vhd
 

diff --git a/cpu/src/extension_uart.vhd b/cpu/src/extension_uart.vhd
new file mode 100644 (file)
index 0000000..9a31d1d
--- /dev/null
+++ b/cpu/src/extension_uart.vhd
@@ -0,0 +1,28 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.extension_uart_pkg.all;
+
+
+entity extension_uart is
+
+       generic (
+                       -- active reset value
+                       RESET_VALUE : std_logic
+                       );
+       port(
+               --System inputs
+                       clk :   in std_logic;
+                       reset : in std_logic;
+               -- general extension interface                  
+                       ext_reg  : in extmod_rec;
+                       data_out : out gp_register_t;
+               -- Input
+
+               -- Ouput
+                       bus_tx : out std_logic
+               );
+               
+end extension_uart;

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
new file mode 100644 (file)
index 0000000..471a9c4
--- /dev/null
+++ b/cpu/src/extension_uart_b.vhd
@@ -0,0 +1,221 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+
+use work.mem_pkg.all;
+use work.extension_uart_pkg.all;
+
+architecture behav of extension_uart is
+
+signal int_rec,int_rec_nxt : extmod_rec;
+signal w1_st_co, w1_st_co_nxt, w2_wewillsee, w2_wewillsee_nxt, w3_wewillsee, w3_wewillsee_nxt, w4_wewillsee, w4_wewillsee_nxt : gp_register_t;
+signal new_tx_data, tx_busy : std_logic;
+
+begin
+
+
+rs232_tx_inst : rs232_tx
+port map(
+       --System inputs
+       clk,
+       reset,
+
+       --Bus
+       bus_tx,
+
+       --From/to sendlogic
+       new_tx_data,
+       w3_wewillsee(byte_t'range),
+       tx_busy
+);
+
+
+
+
+
+syn : process (clk, reset)
+begin
+        if (reset = RESET_VALUE) then
+               int_rec.sel <= '0';
+               int_rec.wr_en <= '0';
+                int_rec.byte_en <= (others=>'0');
+                int_rec.data <= (others=>'0');
+                int_rec.addr <= (others=>'0');
+
+
+        elsif rising_edge(clk) then
+               int_rec <= int_rec_nxt;              
+
+
+        end if;
+end process syn;
+
+-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
+
+gwriten : process (ext_reg)
+
+begin
+       if ext_reg.sel = '1' and ext_reg.wr_en = '1' then
+               int_rec_nxt <= ext_reg;
+       end if;
+end process gwriten;
+
+gread : process (clk,ext_reg)
+
+variable tmp_data  : gp_register_t;
+
+begin
+       if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
+               case ext_reg.addr(1 downto 0) is
+               when "00" => 
+                       tmp_data := (others =>'0');                     
+                       if ext_reg.byte_en(0) = '1' then
+                               tmp_data(byte_t'range) := w1_st_co(byte_t'range);
+                       end if;
+                       if ext_reg.byte_en(1) = '1' then
+                               tmp_data((2*byte_t'length-1) downto byte_t'length) := w1_st_co((2*byte_t'length-1) downto byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(2) = '1' then
+                               tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w1_st_co((3*byte_t'length-1) downto 2*byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(3) = '1' then
+                               tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w1_st_co((4*byte_t'length-1) downto 3*byte_t'length);
+                       end if;
+                       data_out <= tmp_data;
+               when "01" =>
+                       tmp_data := (others =>'0');                     
+                       if ext_reg.byte_en(0) = '1' then
+                               tmp_data(byte_t'range) := w2_wewillsee(byte_t'range);
+                       end if;
+                       if ext_reg.byte_en(1) = '1' then
+                               tmp_data((2*byte_t'length-1) downto byte_t'length) := w2_wewillsee((2*byte_t'length-1) downto byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(2) = '1' then
+                               tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w2_wewillsee((3*byte_t'length-1) downto 2*byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(3) = '1' then
+                               tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w2_wewillsee((4*byte_t'length-1) downto 3*byte_t'length);
+                       end if;
+                       data_out <= tmp_data;
+               when "10" =>
+                       tmp_data := (others =>'0');                     
+                       if ext_reg.byte_en(0) = '1' then
+                               tmp_data(byte_t'range) := w3_wewillsee(byte_t'range);
+                       end if;
+                       if ext_reg.byte_en(1) = '1' then
+                               tmp_data((2*byte_t'length-1) downto byte_t'length) := w3_wewillsee((2*byte_t'length-1) downto byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(2) = '1' then
+                               tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w3_wewillsee((3*byte_t'length-1) downto 2*byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(3) = '1' then
+                               tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w3_wewillsee((4*byte_t'length-1) downto 3*byte_t'length);
+                       end if;
+                       data_out <= tmp_data;
+               when "11" =>
+                       tmp_data := (others =>'0');                     
+                       if ext_reg.byte_en(0) = '1' then
+                               tmp_data(byte_t'range) := w4_wewillsee(byte_t'range);
+                       end if;
+                       if ext_reg.byte_en(1) = '1' then
+                               tmp_data((2*byte_t'length-1) downto byte_t'length) := w4_wewillsee((2*byte_t'length-1) downto byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(2) = '1' then
+                               tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := w4_wewillsee((3*byte_t'length-1) downto 2*byte_t'length);
+                       end if;
+                       if ext_reg.byte_en(3) = '1' then
+                               tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := w4_wewillsee((4*byte_t'length-1) downto 3*byte_t'length);
+                       end if;
+                       data_out <= tmp_data;
+               when others => null;
+               end case;
+       else
+               data_out  <= (others=>'0');             
+       end if;
+end process gread;
+
+proc_data : process (clk,int_rec)
+
+variable tmp_data  : gp_register_t;
+
+begin
+               case int_rec.addr(1 downto 0) is
+               when "00" => 
+                       tmp_data := (others =>'0');                     
+                       if int_rec.byte_en(0) = '1' then
+                               tmp_data(byte_t'range) :=int_rec.data(byte_t'range);
+                       end if;
+                       if int_rec.byte_en(1) = '1' then
+                               tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length);
+                       end if;
+                       if int_rec.byte_en(2) = '1' then
+                               tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length);
+                       end if;
+                       if int_rec.byte_en(3) = '1' then
+                               tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length);
+                       end if;
+                       w1_st_co_nxt <= tmp_data;
+               when "01" =>
+                       tmp_data := (others =>'0');                     
+                       if int_rec.byte_en(0) = '1' then
+                               tmp_data(byte_t'range) := int_rec.data(byte_t'range);
+                       end if;
+                       if int_rec.byte_en(1) = '1' then
+                               tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length);
+                       end if;
+                       if int_rec.byte_en(2) = '1' then
+                               tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length);
+                       end if;
+                       if int_rec.byte_en(3) = '1' then
+                               tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length);
+                       end if;
+                       w2_wewillsee_nxt <= tmp_data;
+               when "10" =>
+                       tmp_data := (others =>'0');                     
+                       if int_rec.byte_en(0) = '1' then
+                                tmp_data(byte_t'range) :=int_rec.data(byte_t'range);
+                       end if;
+                       if int_rec.byte_en(1) = '1' then
+                                tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length);
+                       end if;
+                       if int_rec.byte_en(2) = '1' then
+                                tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length);
+                       end if;
+                       if int_rec.byte_en(3) = '1' then
+                                tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length);
+                       end if;
+                       w3_wewillsee_nxt <= tmp_data;
+               when "11" =>
+                       tmp_data := (others =>'0');                     
+                       if int_rec.byte_en(0) = '1' then
+                                tmp_data(byte_t'range) := w4_wewillsee(byte_t'range);
+                       end if;
+                       if int_rec.byte_en(1) = '1' then
+                                tmp_data((2*byte_t'length-1) downto byte_t'length) := int_rec.data((2*byte_t'length-1) downto byte_t'length);
+                       end if;
+                       if int_rec.byte_en(2) = '1' then
+                                tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := int_rec.data((3*byte_t'length-1) downto 2*byte_t'length);
+                       end if;
+                       if int_rec.byte_en(3) = '1' then
+                                tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := int_rec.data((4*byte_t'length-1) downto 3*byte_t'length);
+                       end if;
+                       w4_wewillsee_nxt <= tmp_data;
+               when others => null;
+               end case;
+end process proc_data;
+
+-------------------------- LESEN UND SCHREIBEN ENDE ---------------------------------------------------------------
+
+-------------------------- INTERNE VERARBEITUNG ANFANG ------------------------------------------------------------
+
+
+
+
+
+-------------------------- INTERNE VERARBEITUNG ENDE --------------------------------------------------------------
+
+end behav;
+

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
new file mode 100644 (file)
index 0000000..fb839ff
--- /dev/null
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -0,0 +1,87 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.common_pkg.all;
+
+
+package extension_uart_pkg is
+
+constant EXTWORDL : integer := log2c(4);
+constant BYTEADDR : integer := log2c(4);
+constant PCOUNT   : integer := 3;
+constant EXTWORDS : integer := EXTWORDL + BYTEADDR;
+
+subtype ext_addrid_t  is std_logic_vector(gp_register_t'high - EXTWORDS downto 0);
+subtype ext_addr_t    is std_logic_vector((gp_register_t'high-BYTEADDR) downto 0);    
+subtype paddr_t is std_logic_vector(log2c(PCOUNT)-1 downto 0);   
+
+        type extmod_rec is record
+                sel   : std_logic;
+                wr_en : std_logic;
+                byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); 
+                data : gp_register_t;
+                addr : ext_addr_t;     
+        end record; 
+
+
+type status_rec is record
+               zero : std_logic;
+               oflo : std_logic;
+               sign : std_logic;
+               carry : std_logic;
+end record;
+
+constant EXT_7SEG_ADDR:   ext_addrid_t := x"FFFFFFA";
+constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
+constant EXT_TIMER_ADDR:  ext_addrid_t := x"FFFFFFC";
+constant EXT_AC97_ADDR:   ext_addrid_t := x"FFFFFFD";
+constant EXT_UART_ADDR:   ext_addrid_t := x"FFFFFFE";
+constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
+--RS232
+constant UART_WIDTH : integer := 8;
+subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
+--CLKs
+constant CLK_FREQ_MHZ : real := 33.33;
+constant BAUD_RATE : integer := 115200;
+constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
+
+ component extension_uart is
+        --some modules won't need all inputs/outputs
+       generic (
+                       -- active reset value
+                       RESET_VALUE : std_logic
+                       );
+       port(
+               --System inputs
+                       clk :   in std_logic;
+                       reset : in std_logic;
+               -- general extension interface                  
+                       ext_reg  : in extmod_rec;
+                       data_out : out gp_register_t;
+               -- Input
+
+               -- Ouput
+                       bus_tx : out std_logic
+               );
+ end component extension_uart;
+
+component rs232_tx is
+
+       port(
+               --System inputs
+               sys_clk : in std_logic;
+               sys_res_n : in std_logic;
+
+               --Bus
+               bus_tx : out std_logic;
+
+               --From/to sendlogic
+               new_tx_data : in std_logic;
+               tx_data : in uart_data;
+               tx_rdy : out std_logic
+       );
+end component rs232_tx;
+
+end package extension_uart_pkg;

diff --git a/cpu/src/rs232_tx.vhd b/cpu/src/rs232_tx.vhd
new file mode 100755 (executable)
index 0000000..d8fb516
--- /dev/null
+++ b/cpu/src/rs232_tx.vhd
@@ -0,0 +1,40 @@
+---------------------------------------------------------------------------------
+-- Filename : rs232_tx.vhd
+-- ========== 
+-- 
+-- Beschreibung : Versand von Daten ueber die RS232 Schnittstelle
+-- ==============
+--
+-- Autoren : Martin Perner, Schwarz Manfred
+-- =========
+----------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use IEEE.std_logic_arith.all;
+
+use work.common_pkg.all;
+use work.core_pkg.all;
+use work.extension_uart_pkg.all;
+
+entity rs232_tx is
+       generic (
+               -- active reset value
+               RESET_VALUE : std_logic
+               );
+       port(
+               --System inputs
+               sys_clk : in std_logic;
+               sys_res_n : in std_logic;
+
+               --Bus
+               bus_tx : out std_logic;
+
+               --From/to sendlogic
+               new_tx_data : in std_logic;
+               tx_data : in uart_data;
+               tx_rdy : out std_logic
+       );
+
+end rs232_tx;

diff --git a/cpu/src/rs232_tx_arc.vhd b/cpu/src/rs232_tx_arc.vhd
new file mode 100755 (executable)
index 0000000..cc29340
--- /dev/null
+++ b/cpu/src/rs232_tx_arc.vhd
@@ -0,0 +1,115 @@
+---------------------------------------------------------------------------------\r
+-- Filename : rs232_tx_arc.vhd\r
+-- ========== \r
+-- \r
+-- Beschreibung : Versand von Daten ueber die RS232 Schnittstelle\r
+-- ==============\r
+--\r
+-- Autoren : Martin Perner, Schwarz Manfred\r
+-- =========\r
+----------------------------------------------------------------------------------\r
+\r
+library IEEE;\r
+use IEEE.std_logic_1164.all;\r
+use IEEE.numeric_std.all;\r
+\r
+use work.common_pkg.all;\r
+use work.core_pkg.all;\r
+use work.extension_uart_pkg.all;\r
+\r
+architecture beh of rs232_tx is\r
+       -- definierern der intern verwendeten Signale\r
+       type STATE_TYPE is (IDLE,SEND);\r
+       signal state, state_next : STATE_TYPE;\r
+       signal bus_tx_int, bus_tx_nxt : std_logic := '1';\r
+       signal baud_cnt,baud_cnt_next : integer := CLK_PER_BAUD;\r
+       signal cnt, cnt_next : natural range 0 to 11 := 0;\r
+       signal idle_sig, idle_sig_next : std_logic := '0';\r
+       \r
+begin\r
+       -- syncronisierungs Prozess\r
+       rs232_tx_syn : process(sys_clk, sys_res_n)\r
+       begin\r
+               if (sys_res_n = RESET_VALUE) then\r
+                       -- reset\r
+                       cnt <= 0;\r
+                       baud_cnt <= 0;\r
+                       state <= IDLE;\r
+                       idle_sig <= '0';\r
+                       bus_tx_int <= '1';\r
+               elsif rising_edge(sys_clk) then\r
+                       -- sync Zustand, uebernehmen der next-Signale\r
+                       baud_cnt <= baud_cnt_next;\r
+                       cnt <= cnt_next;\r
+                       state <= state_next;\r
+                       idle_sig <= idle_sig_next;\r
+                       bus_tx_int <= bus_tx_nxt;\r
+               end if;\r
+       end process;\r
+\r
+       bus_tx <= bus_tx_int;\r
+\r
+       -- Zustandsmaschienen Prozess\r
+       rs232_tx_state : process(state, new_tx_data, idle_sig)\r
+       begin\r
+               state_next <= state;\r
+               case state is\r
+                       when IDLE =>\r
+                               -- wenn neue Sendedaten anliegen wird in den Zustand SEND gewechselt\r
+                               if new_tx_data = '1' then\r
+                                       state_next <= SEND;\r
+                               end if;\r
+                       when SEND =>\r
+                               -- wenn das Byte inklusive Start- und Stopbit versendet wurde, geht \r
+                               -- der Prozess wieder in den IDLE Zustand.\r
+                               if idle_sig = '1' then\r
+                                       state_next <= IDLE;\r
+                               end if;\r
+                       end case;\r
+       end process;\r
+\r
+       -- Ausgabe Logik\r
+       rs232_tx_baud : process(sys_clk, sys_res_n, state, baud_cnt, cnt, tx_data, bus_tx_int)\r
+       begin \r
+               -- Solang idle_sig auf 0 ist wird im SEND Zustand verblieben\r
+               idle_sig_next <= '0';\r
+               bus_tx_nxt <= bus_tx_int;\r
+               cnt_next <= cnt;\r
+               baud_cnt_next <= baud_cnt;\r
+\r
+               case state is\r
+                       when IDLE =>\r
+                               -- tx-Signale im idle Zustand halten\r
+                               tx_rdy <= '1';\r
+                               baud_cnt_next <= CLK_PER_BAUD;\r
+                       when SEND =>\r
+                               -- Signalisiert dass gerade ein Byte versendet wird \r
+                               tx_rdy <= '0';\r
+                               -- Counter erhoehen um die Zeit einer Bitdauer abzuwarten\r
+                               baud_cnt_next <= baud_cnt + 1;\r
+                               if baud_cnt = CLK_PER_BAUD then \r
+                                       -- wenn die Bitdauer erreicht ist, Counter reseten\r
+                                       baud_cnt_next <= 0;\r
+                                       -- Counter um die einzelen Bits zu versenden\r
+                                       cnt_next <= cnt + 1;\r
+                                       case cnt is\r
+                                               when 0 =>\r
+                                                       -- counter = 0 => Startbit versenden\r
+                                                       bus_tx_nxt <= '0';\r
+                                               when 9 =>\r
+                                                       -- counter = 9 => Stopbit versenden\r
+                                                       bus_tx_nxt <= '1';\r
+                                               when 10 =>\r
+                                                       bus_tx_nxt <= '1';\r
+                                                       cnt_next <= 0;\r
+                                                       -- Signalisieren dass der Sendevorgang beendet ist\r
+                                                       idle_sig_next <= '1';\r
+                                               when others =>\r
+                                                       -- counter von 1 bis 8 => Datenbits versenden\r
+                                                       bus_tx_nxt <= tx_data(cnt-1);\r
+                                       end case;\r
+                               end if;\r
+               end case;\r
+       end process;\r
+\r
+end architecture beh;\r