isa: first usable version

diff --git a/2_isa/Makefile b/2_isa/Makefile
index 9a9fcc66debf43b0029f2c1edb1224bac5c415a8..3995bc9ee85c767f4a0dc09530abdc977643a2bc 100644 (file)
--- a/2_isa/Makefile
+++ b/2_isa/Makefile
@@ -4,7 +4,7 @@ FILES  = isa.tex conds.tex
 FILES += Makefile
 TARGET = isa.pdf
 
-ISA_FILES = arith.ptex data.ptex misc.ptex
+ISA_FILES = arith.ptex logic.ptex data.ptex misc.ptex
 
 ISA_BUILD = $(ISA_FILES:.ptex=.tex)
 

diff --git a/2_isa/arith.ptex b/2_isa/arith.ptex
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..eb33a5c4d11dbf7ceaa3b9103391721f749a9afa 100644 (file)
--- a/2_isa/arith.ptex
+++ b/2_isa/arith.ptex
@@ -0,0 +1,13 @@
+ins ('32', 'add', 'Add', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C');
+
+ins ('32', 'addi', 'Add im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | S | C');
+
+ins ('32', 'addx', 'Add im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
+
+ins ('32', 'sub', 'Sub', '4 | 5 | 4 | 4 | 4 | 10 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | - | C');
+
+ins ('32', 'subi', 'Sub im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | S | C');
+
+ins ('32', 'subx', 'Sub im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | S | C');
+
+

diff --git a/2_isa/common.sty b/2_isa/common.sty
index c626b9108810d7d59d4a6bcd547aee3a6ff26ce2..4c55cb1f586874d4aa415b12865256ba79c3530c 100644 (file)
--- a/2_isa/common.sty
+++ b/2_isa/common.sty
@@ -6,6 +6,16 @@
 \usepackage{listings}
 \usepackage{ngerman}
 
+%used for coloring of instr.
+\usepackage{colortbl}
+
+\definecolor{title}{rgb}{0.86,0.86,0.86}
+\definecolor{bit}{rgb}{0.8,0.86,0.8}
+\definecolor{bitval}{rgb}{0.8,0.8,0.8}
+\definecolor{names}{rgb}{0.86,0.93,0.86}
+
+\arrayrulecolor{black}
+
 
 % put footnotes below floats
 % this is a good idea if the table for the cmp looks bad on top of page

diff --git a/2_isa/conds.tex b/2_isa/conds.tex
index 3f827364dade4bf66a2618491c20993a6bdc03c1..1ab5cc48d7923342fcce31508dc59d45e293ccfa 100644 (file)
--- a/2_isa/conds.tex
+++ b/2_isa/conds.tex
@@ -3,25 +3,25 @@
 \begin{table}[ht]
        \centering
        \begin{tabular}{|c|c|c|}\hline
-               Bitcode & Condition             & Bits to test \\ \hline
-               0000    & equal / zero          & ZF = 0\\ \hline
-               0001    & not equal / not zero  & ZF = 1\\ \hline
-               0010    & not overflow          & OF = 0\\ \hline
-               0011    & overflow              & OF = 1\\ \hline
-               0100    & not carry             & CF = 0\\ \hline
-               0101    & carry                 & CF = 1\\ \hline
-               0110    & not signed / not neg. & SF = 0\\ \hline
-               0111    & signed / neg.         & SF = 1\\ \hline
-               1000    & below (?)             & \\ \hline
-               1001    & above (?)             & \\ \hline
-               1010    & greater than or equal & SF == OF\\ \hline
-               1011    & less than             & SF != OF \\ \hline
-               1100    & greater than          & (ZF == 0 $\wedge$ SF == OF) \\ \hline
-               1101    & less than or equal    & (ZF == 1 $\vee$ SF != OF) \\ \hline
-               1110    & never                 & \\ \hline
-               1111    & always                & \\ \hline
+               Bitcode & Condition               & Bits to test \\ \hline
+               0000    & equal / zero            & ZF = 0\\ \hline
+               0001    & not equal / not zero    & ZF = 1\\ \hline
+               0010    & not overflow            & OF = 0\\ \hline
+               0011    & overflow                & OF = 1\\ \hline
+               0100    & not carry / below       & CF = 0\\ \hline
+               0101    & carry / above or equal  & CF = 1\\ \hline
+               0110    & not signed / not neg.   & SF = 0\\ \hline
+               0111    & signed / neg.           & SF = 1\\ \hline
+               1000    & above                   & (CF == 0 $\wedge$ ZF ==  0)\\ \hline
+               1001    & below or equal          & (CF == 1 $\vee$ ZF == 1) \\ \hline
+               1010    & greater than or equal   & SF == OF\\ \hline
+               1011    & less than               & SF != OF \\ \hline
+               1100    & greater than            & (ZF == 0 $\wedge$ SF == OF) \\ \hline
+               1101    & less than or equal      & (ZF == 1 $\vee$ SF != OF) \\ \hline
+               1110    & never                   & \\ \hline
+               1111    & always                  & \\ \hline
        \end{tabular}
-       \caption{codierung von conditions}
+       \caption{codierung von conditions WARNING! may contain BUGS!!}
 \end{table}
 
 \begin{table}

diff --git a/2_isa/data.ptex b/2_isa/data.ptex
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..0dbde7543fbc965b9883195c26b9113149c69a92 100644 (file)
--- a/2_isa/data.ptex
+++ b/2_isa/data.ptex
@@ -0,0 +1,26 @@
+ins ('32', 'movpf', 'Move from PSW', '4 | 5 | 4 | 19', 'Conditions | OpCode | Register Destination| - ');
+
+ins ('32', 'movpt', 'Move to PSW', '4 | 5 | 4 | 19', 'Conditions | OpCode | Register Source| - ');
+
+ins ('32', 'ldw', 'Load word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment? ');
+ins ('32', 'ldh', 'Load half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment? ');
+ins ('32', 'ldb', 'Load byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment? ');
+
+ins ('32', 'ldi', 'Load immediate', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | - | h/l | S ');
+
+ins ('32', 'stw', 'store word; needs to be aligned to 32bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| - ');
+ins ('32', 'sth', 'store half word; needs to be aligned to 16bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| - ');
+ins ('32', 'stb', 'store byte, 8bit', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| - ');
+
+ins ('32', 'ldx', 'Load from programspace', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacment ');
+
+ins ('32', 'stx', 'Store to programspace', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register Destination|Register Address| displacement ');
+
+
+ins ('32', 'pop', 'pop from stack', '4 | 5 | 4 | 19', 'Conditions | OpCode | Register Destination | - ');
+
+ins ('32', 'push', 'push to stack', '4 | 5 | 4 |  19', 'Conditions | OpCode | Register Source | - ');
+
+ins ('32', 'disc', 'discard top-element from stack', '4 | 5 |  23', 'Conditions | OpCode | - ');
+
+ins ('32', 'fetch', 'get top-element from stack', '4 | 5 | 4 |  19', 'Conditions | OpCode | Register Destination | - ');

diff --git a/2_isa/isa.tex b/2_isa/isa.tex
index 73e462bedbe7dbb1b5ae3b4b06c59d0df837dbd9..845454945327ee0a95208e6935f37caf370d2321 100644 (file)
--- a/2_isa/isa.tex
+++ b/2_isa/isa.tex
@@ -14,14 +14,34 @@
 \tableofcontents
 \newpage
 
-\include{conds}
+\input{conds}
+if a condition is not met, the instruction is executed but no changes (on data or flags) occure.
 \section{instr}
+
 \subsection{arith}
-\include{arith}
+modifies all flags
+\input{arith}
+
+\subsection{logic}
+modifies zero and sign flag only. shifts may modify carry
+
+rotate?!?!?!?
+
+C is for shift to desc. a shift through carry
+F is for fill the unused
+ARITH makes logic right shift to arithemtic right shift
+
+not kann durch xorif rD, rS, \#0x7FF ersetzt werden. makro \_NOT daf\"ur.
+
+\input{logic}
+
 \subsection{data}
-\include{data}
+
+use addi rD, rS, \#0 for mov rD, rS \\
+
+\input{data}
 \subsection{misc}
-\include{misc}
+\input{misc}
 
 
 \end{document}

diff --git a/2_isa/logic.ptex b/2_isa/logic.ptex
new file mode 100644 (file)
index 0000000..4d6b7f0
--- /dev/null
+++ b/2_isa/logic.ptex
@@ -0,0 +1,23 @@
+
+
+ins ('32', 'and', 'And', '4 | 5 | 4 | 4 | 4 | 11', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | -');
+
+ins ('32', 'andi', 'And im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
+
+ins ('32', 'andx', 'And im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | -');
+
+ins ('32', 'or', 'Or', '4 | 5 | 4 | 4 | 4 | 11', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | -');
+
+ins ('32', 'ori', 'Or im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
+
+ins ('32', 'orx', 'Or im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | -');
+
+ins ('32', 'xor', 'Or', '4 | 5 | 4 | 4 | 4 | 11', 'Conditions | OpCode | Register Destination|Register A (Source1)| Register B (Source2) | -');
+
+ins ('32', 'xori', 'Xor im', '4 | 5 | 4 | 4 | 12 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | H/L | F | -');
+
+ins ('32', 'xorx', 'Xor im 16bit', '4 | 5 | 4 | 16 | 1 | 1 | 1', 'Conditions | OpCode | Register Destination| Immediate | H/L | F | -');
+
+ins ('32', 'lls', 'left shift', '4 | 5 | 4 | 4 | 5 | 9 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | C');
+
+ins ('32', 'lrs', 'right shift', '4 | 5 | 4 | 4 | 5 | 8 | 1 | 1', 'Conditions | OpCode | Register Destination|Register A (Source1)| Immediate | - | ARITH | C');

diff --git a/2_isa/misc.ptex b/2_isa/misc.ptex
index e69de29bb2d1d6434b8b29ae775ad8c2e48c5391..3942fb59104fc506ae601acdafade9ba690c0143 100644 (file)
--- a/2_isa/misc.ptex
+++ b/2_isa/misc.ptex
@@ -0,0 +1,11 @@
+ins ('32', 'branch', 'Branch; save pc+1 in stack, jump to pc+imm', '4 | 5 | 16 | 5 | 1 | 1', 'Conditions | OpCode | Immediate | - | +/- | S');
+
+ins ('32', 'jump', 'Jump; jump to pc+imm', '4 | 5 | 16 | 5 | 1 | 1', 'Conditions | OpCode | Immediate | - | +/- | S');
+
+ins ('32', 'ret', 'ret', '4 | 5 | 23 ', 'Conditions | OpCode | -');
+
+ins ('32', 'reti', 'reti', '4 | 5 | 23 ', 'Conditions | OpCode | -');
+
+ins ('32', 'cmp', 'compare (rS1 - rS2)', '4 | 5 | 4 | 4 | 15', 'Conditions | OpCode | Register A (Source1) | Register B (Source2) | -');
+
+ins ('32', 'cmpi', 'compare (rS1 - imm)', '4 | 5 |  4 | 16 | 3', 'Conditions | OpCode | Register A (Source1) | Immediate | -');