Analysis & Synthesis report for dt
-Fri Dec 17 12:26:49 2010
+Sun Dec 19 20:36:26 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
14. Inverted Register Statistics
15. Registers Packed Into Inferred Megafunctions
16. Multiplexer Restructuring Statistics (Restructuring Performed)
- 17. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated
+ 17. Source assignments for writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated
18. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated
- 19. Parameter Settings for User Entity Instance: fetch_stage:fetch_st
- 20. Parameter Settings for User Entity Instance: fetch_stage:fetch_st|r_w_ram:instruction_ram
- 21. Parameter Settings for User Entity Instance: decode_stage:decode_st
- 22. Parameter Settings for User Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram
- 23. Parameter Settings for User Entity Instance: execute_stage:exec_st
- 24. Parameter Settings for User Entity Instance: execute_stage:exec_st|extension_gpm:gpmp_inst
- 25. Parameter Settings for User Entity Instance: writeback_stage:writeback_st
- 26. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram
- 27. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart
- 28. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst
- 29. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst
- 30. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0
- 31. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1
- 32. altsyncram Parameter Settings by Entity Instance
- 33. Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst"
- 34. Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart"
- 35. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
- 36. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
- 37. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
- 38. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
- 39. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
- 40. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst"
- 41. Port Connectivity Checks: "execute_stage:exec_st"
- 42. Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst"
- 43. Analysis & Synthesis Messages
+ 19. Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated
+ 20. Parameter Settings for User Entity Instance: fetch_stage:fetch_st
+ 21. Parameter Settings for User Entity Instance: fetch_stage:fetch_st|rom:instruction_ram
+ 22. Parameter Settings for User Entity Instance: decode_stage:decode_st
+ 23. Parameter Settings for User Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram
+ 24. Parameter Settings for User Entity Instance: execute_stage:exec_st
+ 25. Parameter Settings for User Entity Instance: execute_stage:exec_st|extension_gpm:gpmp_inst
+ 26. Parameter Settings for User Entity Instance: writeback_stage:writeback_st
+ 27. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram
+ 28. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart
+ 29. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst
+ 30. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst
+ 31. Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_7seg:sseg
+ 32. Parameter Settings for Inferred Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0
+ 33. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1
+ 34. Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2
+ 35. altsyncram Parameter Settings by Entity Instance
+ 36. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
+ 37. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:xor_inst"
+ 38. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:or_inst"
+ 39. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:and_inst"
+ 40. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst|exec_op:add_inst"
+ 41. Port Connectivity Checks: "execute_stage:exec_st|alu:alu_inst"
+ 42. Port Connectivity Checks: "execute_stage:exec_st"
+ 43. Port Connectivity Checks: "decode_stage:decode_st|decoder:decoder_inst"
+ 44. Analysis & Synthesis Messages
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
-; Analysis & Synthesis Status ; Successful - Fri Dec 17 12:26:49 2010 ;
+; Analysis & Synthesis Status ; Successful - Sun Dec 19 20:36:26 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
-; Total logic elements ; 1,143 ;
-; Total pins ; 3 ;
+; Total logic elements ; 1,879 ;
+; Total pins ; 32 ;
; Total virtual pins ; 0 ;
-; Total memory bits ; 512 ;
+; Total memory bits ; 66,560 ;
; Total PLLs ; 0 ;
+-----------------------------+-----------------------------------------------+
+----------------------------+--------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Source Files Read ;
-+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
-; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
-+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
-; ../cpu/src/rs232_rx_arc.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_rx_arc.vhd ;
-; ../cpu/src/rs232_rx.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_rx.vhd ;
-; ../cpu/src/writeback_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/writeback_stage_b.vhd ;
-; ../cpu/src/writeback_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/writeback_stage.vhd ;
-; ../cpu/src/rs232_tx_arc.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_tx_arc.vhd ;
-; ../cpu/src/rs232_tx.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/rs232_tx.vhd ;
-; ../cpu/src/r_w_ram_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r_w_ram_b.vhd ;
-; ../cpu/src/r_w_ram.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r_w_ram.vhd ;
-; ../cpu/src/r2_w_ram_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r2_w_ram_b.vhd ;
-; ../cpu/src/r2_w_ram.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/r2_w_ram.vhd ;
-; ../cpu/src/mem_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/mem_pkg.vhd ;
-; ../cpu/src/fetch_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/fetch_stage_b.vhd ;
-; ../cpu/src/fetch_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/fetch_stage.vhd ;
-; ../cpu/src/extension_uart_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_uart_pkg.vhd ;
-; ../cpu/src/extension_uart_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_uart_b.vhd ;
-; ../cpu/src/extension_uart.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_uart.vhd ;
-; ../cpu/src/extension_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_pkg.vhd ;
-; ../cpu/src/extension_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension_b.vhd ;
-; ../cpu/src/extension.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/extension.vhd ;
-; ../cpu/src/execute_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/execute_stage_b.vhd ;
-; ../cpu/src/execute_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/execute_stage.vhd ;
-; ../cpu/src/exec_op.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op.vhd ;
-; ../cpu/src/decoder_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decoder_b.vhd ;
-; ../cpu/src/decoder.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decoder.vhd ;
-; ../cpu/src/decode_stage_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decode_stage_b.vhd ;
-; ../cpu/src/decode_stage.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/decode_stage.vhd ;
-; ../cpu/src/core_top.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/core_top.vhd ;
-; ../cpu/src/core_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/core_pkg.vhd ;
-; ../cpu/src/common_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/common_pkg.vhd ;
-; ../cpu/src/alu_pkg.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/alu_pkg.vhd ;
-; ../cpu/src/alu_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/alu_b.vhd ;
-; ../cpu/src/alu.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/alu.vhd ;
-; ../cpu/src/exec_op/xor_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/xor_op_b.vhd ;
-; ../cpu/src/exec_op/shift_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/shift_op_b.vhd ;
-; ../cpu/src/exec_op/or_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/or_op_b.vhd ;
-; ../cpu/src/exec_op/and_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/and_op_b.vhd ;
-; ../cpu/src/exec_op/add_op_b.vhd ; yes ; User VHDL File ; /homes/c0726283/calu/cpu/src/exec_op/add_op_b.vhd ;
-; altsyncram.tdf ; yes ; Megafunction ; /opt/altera/10.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ;
-; db/altsyncram_emk1.tdf ; yes ; Auto-Generated Megafunction ; /homes/c0726283/calu/dt/db/altsyncram_emk1.tdf ;
-; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /homes/c0726283/calu/dt/db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
-+--------------------------------------+-----------------+-------------------------------------------------------+--------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++--------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++--------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------+
+; ../cpu/src/rom.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rom.vhd ;
+; ../cpu/src/rom_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rom_b.vhd ;
+; ../cpu/src/extension_7seg_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_7seg_pkg.vhd ;
+; ../cpu/src/extension_7seg_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_7seg_b.vhd ;
+; ../cpu/src/extension_7seg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_7seg.vhd ;
+; ../cpu/src/rs232_rx_arc.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_rx_arc.vhd ;
+; ../cpu/src/rs232_rx.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_rx.vhd ;
+; ../cpu/src/writeback_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/writeback_stage_b.vhd ;
+; ../cpu/src/writeback_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/writeback_stage.vhd ;
+; ../cpu/src/rs232_tx_arc.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_tx_arc.vhd ;
+; ../cpu/src/rs232_tx.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/rs232_tx.vhd ;
+; ../cpu/src/r_w_ram_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r_w_ram_b.vhd ;
+; ../cpu/src/r_w_ram.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r_w_ram.vhd ;
+; ../cpu/src/r2_w_ram_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r2_w_ram_b.vhd ;
+; ../cpu/src/r2_w_ram.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/r2_w_ram.vhd ;
+; ../cpu/src/mem_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/mem_pkg.vhd ;
+; ../cpu/src/fetch_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd ;
+; ../cpu/src/fetch_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/fetch_stage.vhd ;
+; ../cpu/src/extension_uart_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_uart_pkg.vhd ;
+; ../cpu/src/extension_uart_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_uart_b.vhd ;
+; ../cpu/src/extension_uart.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_uart.vhd ;
+; ../cpu/src/extension_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_pkg.vhd ;
+; ../cpu/src/extension_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension_b.vhd ;
+; ../cpu/src/extension.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/extension.vhd ;
+; ../cpu/src/execute_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/execute_stage_b.vhd ;
+; ../cpu/src/execute_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/execute_stage.vhd ;
+; ../cpu/src/exec_op.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op.vhd ;
+; ../cpu/src/decoder_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decoder_b.vhd ;
+; ../cpu/src/decoder.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decoder.vhd ;
+; ../cpu/src/decode_stage_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decode_stage_b.vhd ;
+; ../cpu/src/decode_stage.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/decode_stage.vhd ;
+; ../cpu/src/core_top.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/core_top.vhd ;
+; ../cpu/src/core_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/core_pkg.vhd ;
+; ../cpu/src/common_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/common_pkg.vhd ;
+; ../cpu/src/alu_pkg.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/alu_pkg.vhd ;
+; ../cpu/src/alu_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/alu_b.vhd ;
+; ../cpu/src/alu.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/alu.vhd ;
+; ../cpu/src/exec_op/xor_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/xor_op_b.vhd ;
+; ../cpu/src/exec_op/shift_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/shift_op_b.vhd ;
+; ../cpu/src/exec_op/or_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/or_op_b.vhd ;
+; ../cpu/src/exec_op/and_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/and_op_b.vhd ;
+; ../cpu/src/exec_op/add_op_b.vhd ; yes ; User VHDL File ; /home/stefan/processor/calu/cpu/src/exec_op/add_op_b.vhd ;
+; altsyncram.tdf ; yes ; Megafunction ; /opt/altera/10.0sp1/quartus/libraries/megafunctions/altsyncram.tdf ;
+; db/altsyncram_grk1.tdf ; yes ; Auto-Generated Megafunction ; /home/stefan/processor/calu/dt/db/altsyncram_grk1.tdf ;
+; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /home/stefan/processor/calu/dt/db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ;
+; db/altsyncram_emk1.tdf ; yes ; Auto-Generated Megafunction ; /home/stefan/processor/calu/dt/db/altsyncram_emk1.tdf ;
+; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; yes ; Auto-Generated Auto-Found Memory Initialization File ; /home/stefan/processor/calu/dt/db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
++--------------------------------------+-----------------+-------------------------------------------------------+---------------------------------------------------------------------+
+-------------------------------------------------------+
+---------------------------------------------+---------+
; Resource ; Usage ;
+---------------------------------------------+---------+
-; Total logic elements ; 1143 ;
-; -- Combinational with no register ; 928 ;
-; -- Register only ; 85 ;
-; -- Combinational with a register ; 130 ;
+; Total logic elements ; 1879 ;
+; -- Combinational with no register ; 1359 ;
+; -- Register only ; 259 ;
+; -- Combinational with a register ; 261 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 473 ;
-; -- 3 input functions ; 443 ;
-; -- 2 input functions ; 123 ;
-; -- 1 input functions ; 18 ;
-; -- 0 input functions ; 1 ;
+; -- 4 input functions ; 827 ;
+; -- 3 input functions ; 474 ;
+; -- 2 input functions ; 292 ;
+; -- 1 input functions ; 27 ;
+; -- 0 input functions ; 0 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 937 ;
-; -- arithmetic mode ; 206 ;
+; -- normal mode ; 1703 ;
+; -- arithmetic mode ; 176 ;
; -- qfbk mode ; 0 ;
; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 7 ;
-; -- asynchronous clear/load mode ; 203 ;
+; -- synchronous clear/load mode ; 57 ;
+; -- asynchronous clear/load mode ; 492 ;
; ; ;
-; Total registers ; 215 ;
-; Total logic cells in carry chains ; 214 ;
-; I/O pins ; 3 ;
-; Total memory bits ; 512 ;
+; Total registers ; 520 ;
+; Total logic cells in carry chains ; 184 ;
+; I/O pins ; 32 ;
+; Total memory bits ; 66560 ;
; Maximum fan-out node ; sys_clk ;
-; Maximum fan-out ; 279 ;
-; Total fan-out ; 4464 ;
-; Average fan-out ; 3.69 ;
+; Maximum fan-out ; 616 ;
+; Total fan-out ; 8075 ;
+; Average fan-out ; 4.02 ;
+---------------------------------------------+---------+
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis Resource Utilization by Entity ;
-+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
-+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 1143 (1) ; 215 ; 512 ; 3 ; 0 ; 928 (1) ; 85 (0) ; 130 (0) ; 214 (0) ; 0 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 106 (99) ; 72 ; 512 ; 0 ; 0 ; 34 (27) ; 51 (51) ; 21 (21) ; 11 (11) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
-; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
-; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
-; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 831 (185) ; 67 ; 0 ; 0 ; 0 ; 764 (149) ; 20 (1) ; 47 (35) ; 171 (0) ; 0 (0) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 581 (259) ; 0 ; 0 ; 0 ; 0 ; 581 (259) ; 0 (0) ; 0 (0) ; 141 (43) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
-; |exec_op:add_inst| ; 100 (100) ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 0 (0) ; 0 (0) ; 98 (98) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |exec_op:or_inst| ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
-; |exec_op:shift_inst| ; 208 (208) ; 0 ; 0 ; 0 ; 0 ; 208 (208) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
-; |extension_gpm:gpmp_inst| ; 65 (65) ; 31 ; 0 ; 0 ; 0 ; 34 (34) ; 19 (19) ; 12 (12) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
-; |fetch_stage:fetch_st| ; 39 (30) ; 17 ; 0 ; 0 ; 0 ; 22 (19) ; 11 (11) ; 6 (0) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
-; |r_w_ram:instruction_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 166 (49) ; 59 ; 0 ; 0 ; 0 ; 107 (45) ; 3 (1) ; 56 (3) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
-; |extension_uart:uart| ; 108 (14) ; 49 ; 0 ; 0 ; 0 ; 59 (4) ; 2 (2) ; 47 (8) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
-; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
-; |r_w_ram:data_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
-+----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
+; |core_top ; 1879 (0) ; 520 ; 66560 ; 32 ; 0 ; 1359 (0) ; 259 (0) ; 261 (0) ; 184 (0) ; 0 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 220 (153) ; 106 ; 1024 ; 0 ; 0 ; 114 (47) ; 54 (54) ; 52 (52) ; 11 (11) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 67 (67) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 1024 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
+; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
+; |altsyncram:ram_rtl_2| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated ; ;
+; |execute_stage:exec_st| ; 940 (175) ; 71 ; 0 ; 0 ; 0 ; 869 (136) ; 23 (4) ; 48 (35) ; 108 (0) ; 0 (0) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 703 (387) ; 0 ; 0 ; 0 ; 0 ; 703 (387) ; 0 (0) ; 0 (0) ; 78 (44) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |exec_op:add_inst| ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 67 (67) ; 0 (0) ; 0 (0) ; 34 (34) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
+; |exec_op:shift_inst| ; 249 (249) ; 0 ; 0 ; 0 ; 0 ; 249 (249) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
+; |extension_gpm:gpmp_inst| ; 62 (62) ; 32 ; 0 ; 0 ; 0 ; 30 (30) ; 19 (19) ; 13 (13) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
+; |fetch_stage:fetch_st| ; 55 (34) ; 29 ; 0 ; 0 ; 0 ; 26 (23) ; 11 (11) ; 18 (0) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
+; |rom:instruction_ram| ; 21 (21) ; 18 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 18 (18) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|rom:instruction_ram ; ;
+; |writeback_stage:writeback_st| ; 664 (247) ; 314 ; 65536 ; 0 ; 0 ; 350 (183) ; 171 (45) ; 143 (19) ; 65 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
+; |extension_7seg:sseg| ; 48 (48) ; 47 ; 0 ; 0 ; 0 ; 1 (1) ; 18 (18) ; 29 (29) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_7seg:sseg ; ;
+; |extension_uart:uart| ; 369 (145) ; 203 ; 0 ; 0 ; 0 ; 166 (39) ; 108 (98) ; 95 (8) ; 65 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
+; |rs232_rx:rs232_rx_inst| ; 160 (160) ; 73 ; 0 ; 0 ; 0 ; 87 (87) ; 10 (10) ; 63 (63) ; 48 (48) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst ; ;
+; |rs232_tx:rs232_tx_inst| ; 64 (64) ; 24 ; 0 ; 0 ; 0 ; 40 (40) ; 0 (0) ; 24 (24) ; 17 (17) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
+; |r_w_ram:data_ram| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ; ;
+; |altsyncram_grk1:auto_generated| ; 0 (0) ; 0 ; 65536 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated ; ;
++----------------------------------------------+-------------+--------------+-------------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Analysis & Synthesis RAM Summary ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------------------------+
-; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------------------------+
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+------+--------------------------------------+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis RAM Summary ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
+; Name ; Type ; Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 16 ; 32 ; 16 ; 32 ; 512 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; 2048 ; 32 ; 2048 ; 32 ; 65536 ; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+-------+--------------------------------------+
Encoding Type: One-Hot
+--------------------------------+--------------------------------+-----------------------------+------------------------------+-------------------------------+-----------------------------+----------------------------+-----------------------------+--------------------------------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Registers Removed During Synthesis ;
-+------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-; Register name ; Reason for Removal ;
-+------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-; writeback_stage:writeback_st|bus_rx ; Stuck at VCC due to stuck port data_in ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; Lost fanout ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[29..31] ; Stuck at VCC due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[24] ; Stuck at VCC due to stuck port data_in ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[0,2,5,8,10..15,17..18,20,22] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.prog_cnt[11..31] ; Stuck at GND due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29..31] ; Stuck at VCC due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[28] ; Stuck at GND due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24] ; Stuck at VCC due to stuck port data_in ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0,2,5,8,10..15,17..18,20,22] ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.hword ; Stuck at GND due to stuck port data_in ;
-; writeback_stage:writeback_st|wb_reg.byte_s ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.condition[1..3] ; Stuck at VCC due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.op_detail[5] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.displacement[0,2,5,8,10..31] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.saddr1[3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.saddr2[1,3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|dec_op_inst.daddr[1,3] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|reg.res_addr[1,3] ; Stuck at GND due to stuck port data_in ;
-; decode_stage:decode_st|rtw_rec.immediate[5,7..8,10..11,15] ; Stuck at GND due to stuck port data_in ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1] ; Lost fanout ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0] ; Lost fanout ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[23] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[1] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[4,6] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[19] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[3] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ;
-; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[7] ; Merged with writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ;
-; decode_stage:decode_st|dec_op_inst.op_detail[0] ; Merged with decode_stage:decode_st|rtw_rec.imm_set ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[23] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[1] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[4,6] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[19] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[3] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[16] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[7] ; Merged with fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[9] ;
-; decode_stage:decode_st|dec_op_inst.daddr[2] ; Lost fanout ;
-; execute_stage:exec_st|reg.res_addr[0] ; Merged with execute_stage:exec_st|reg.res_addr[2] ;
-; decode_stage:decode_st|rtw_rec.immediate[18,21,23..28,30] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
-; decode_stage:decode_st|rtw_rec.immediate[16] ; Merged with decode_stage:decode_st|rtw_rec.immediate[29] ;
-; decode_stage:decode_st|rtw_rec.immediate[20] ; Merged with decode_stage:decode_st|rtw_rec.immediate[22] ;
-; decode_stage:decode_st|rtw_rec.immediate[17] ; Merged with decode_stage:decode_st|rtw_rec.immediate[19] ;
-; decode_stage:decode_st|rtw_rec.immediate[12] ; Merged with decode_stage:decode_st|rtw_rec.immediate[14] ;
-; decode_stage:decode_st|rtw_rec.immediate[1] ; Merged with decode_stage:decode_st|rtw_rec.immediate[3] ;
-; decode_stage:decode_st|dec_op_inst.displacement[7] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[9] ;
-; decode_stage:decode_st|dec_op_inst.displacement[4] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[6] ;
-; decode_stage:decode_st|dec_op_inst.saddr1[0] ; Merged with decode_stage:decode_st|dec_op_inst.saddr1[2] ;
-; decode_stage:decode_st|dec_op_inst.saddr2[0] ; Merged with decode_stage:decode_st|dec_op_inst.saddr2[2] ;
-; decode_stage:decode_st|dec_op_inst.op_detail[1] ; Merged with decode_stage:decode_st|dec_op_inst.op_detail[2] ;
-; decode_stage:decode_st|rtw_rec.immediate[19,22,29] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
-; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; Lost fanout ;
-; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[0..31] ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0..31] ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.IDLE ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; Lost fanout ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.POST_STOP ; Lost fanout ;
-; decode_stage:decode_st|rtw_rec.immediate[31] ; Merged with decode_stage:decode_st|dec_op_inst.op_group.OR_OP ;
-; decode_stage:decode_st|rtw_rec.immediate[9] ; Merged with decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ;
-; fetch_stage:fetch_st|instr_r_addr[11..31] ; Lost fanout ;
-; Total Number of Removed Registers = 332 ; ;
-+------------------------------------------------------------------------------------------+------------------------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Removed Registers Triggering Further Register Optimizations ;
-+-----------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------+
-; Register name ; Reason for Removal ; Registers Removed due to This Register ;
-+-----------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------+
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[24] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.op_detail[5], ;
-; ; due to stuck port data_in ; decode_stage:decode_st|dec_op_inst.saddr1[3], ;
-; ; ; decode_stage:decode_st|dec_op_inst.saddr2[3], ;
-; ; ; decode_stage:decode_st|dec_op_inst.saddr2[1], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[15], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[11], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[10], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[8], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[7], ;
-; ; ; decode_stage:decode_st|rtw_rec.immediate[5] ;
-; writeback_stage:writeback_st|bus_rx ; Stuck at VCC ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[31], ;
-; ; due to stuck port data_in ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[30], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[29], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[28], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[27], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[26], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[25], ;
-; ; ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[24] ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[31] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[3], ;
-; ; due to stuck port data_in ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo, ;
-; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[22] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[3], execute_stage:exec_st|reg.res_addr[3] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[20] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.daddr[1], execute_stage:exec_st|reg.res_addr[1] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[30] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[2] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[29] ; Stuck at VCC ; decode_stage:decode_st|dec_op_inst.condition[1] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[14] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[14] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[13] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[13] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[12] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[12] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[11] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[11] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[10] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[10] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[8] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[8] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[5] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[5] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[2] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[2] ;
-; ; due to stuck port data_in ; ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[0] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[0] ;
-; ; due to stuck port data_in ; ;
-+-----------------------------------------------------------+---------------------------+---------------------------------------------------------------------------------------+
++------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Registers Removed During Synthesis ;
++------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
+; Register name ; Reason for Removal ;
++------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
+; decode_stage:decode_st|dec_op_inst.prog_cnt[11..31] ; Stuck at GND due to stuck port data_in ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[2,8] ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.hword ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.byte_s ; Stuck at GND due to stuck port data_in ;
+; writeback_stage:writeback_st|wb_reg.address[0..1] ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.displacement[2,8] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][0] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[2][0] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][29] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][28] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][27] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][26] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][25] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][24] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][23] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][22] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][21] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][20] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][19] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][18] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][17] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][16] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][15] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][14] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][13] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][12] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][11] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][10] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][9] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][8] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][7] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][6] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][5] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][4] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][3] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1] ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0] ; Lost fanout ;
+; writeback_stage:writeback_st|wb_reg.byte_en[0..3] ; Merged with writeback_stage:writeback_st|wb_reg.dmem_en ;
+; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.byte_en[0] ; Merged with writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.byte_en[1] ;
+; writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[8..30] ; Merged with writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[31] ;
+; decode_stage:decode_st|dec_op_inst.op_detail[0] ; Merged with decode_stage:decode_st|rtw_rec.imm_set ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[9,28..30] ; Merged with fetch_stage:fetch_st|rom:instruction_ram|data_out[31] ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[0,10..14,18] ; Merged with fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[3] ; Merged with fetch_stage:fetch_st|rom:instruction_ram|data_out[4] ;
+; decode_stage:decode_st|rtw_rec.immediate[23..27] ; Merged with decode_stage:decode_st|rtw_rec.immediate[31] ;
+; decode_stage:decode_st|rtw_rec.immediate[16] ; Merged with decode_stage:decode_st|rtw_rec.immediate[17] ;
+; decode_stage:decode_st|rtw_rec.immediate[7] ; Merged with decode_stage:decode_st|rtw_rec.immediate[11] ;
+; decode_stage:decode_st|dec_op_inst.condition[1..2] ; Merged with decode_stage:decode_st|dec_op_inst.condition[3] ;
+; decode_stage:decode_st|dec_op_inst.displacement[15..30] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[31] ;
+; decode_stage:decode_st|dec_op_inst.displacement[0,10..13] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[14] ;
+; decode_stage:decode_st|dec_op_inst.displacement[3] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[4] ;
+; writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[31] ; Stuck at GND due to stuck port data_in ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; Lost fanout ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ; Lost fanout ;
+; decode_stage:decode_st|dec_op_inst.displacement[14] ; Merged with decode_stage:decode_st|dec_op_inst.displacement[31] ;
+; fetch_stage:fetch_st|instr_r_addr[11..31] ; Lost fanout ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17..31] ; Lost fanout ;
+; Total Number of Removed Registers = 231 ; ;
++------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------+
+
+
++------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Removed Registers Triggering Further Register Optimizations ;
++---------------------------------------------------------------+---------------------------+----------------------------------------------------------------+
+; Register name ; Reason for Removal ; Registers Removed due to This Register ;
++---------------------------------------------------------------+---------------------------+----------------------------------------------------------------+
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29] ; Lost Fanouts ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo, ;
+; ; ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[8] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[8] ;
+; ; due to stuck port data_in ; ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[2] ; Stuck at GND ; decode_stage:decode_st|dec_op_inst.displacement[2] ;
+; ; due to stuck port data_in ; ;
++---------------------------------------------------------------+---------------------------+----------------------------------------------------------------+
+------------------------------------------------------+
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
-; Total registers ; 215 ;
-; Number of registers using Synchronous Clear ; 4 ;
-; Number of registers using Synchronous Load ; 6 ;
-; Number of registers using Asynchronous Clear ; 192 ;
-; Number of registers using Asynchronous Load ; 11 ;
-; Number of registers using Clock Enable ; 43 ;
+; Total registers ; 520 ;
+; Number of registers using Synchronous Clear ; 25 ;
+; Number of registers using Synchronous Load ; 40 ;
+; Number of registers using Asynchronous Clear ; 487 ;
+; Number of registers using Asynchronous Load ; 5 ;
+; Number of registers using Clock Enable ; 177 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
-+------------------------------------------------------------------------------------------------+
-; Inverted Register Statistics ;
-+--------------------------------------------------------------------------------------+---------+
-; Inverted Register ; Fan out ;
-+--------------------------------------------------------------------------------------+---------+
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 1 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 2 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 2 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 2 ;
-; decode_stage:decode_st|dec_op_inst.condition[0] ; 1 ;
-; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 4 ;
-; Total number of inverted registers = 24 ; ;
-+--------------------------------------------------------------------------------------+---------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------+
-; Registers Packed Into Inferred Megafunctions ;
-+------------------------------------------------------------+-----------------------------------------------------+------+
-; Register Name ; Megafunction ; Type ;
-+------------------------------------------------------------+-----------------------------------------------------+------+
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
-+------------------------------------------------------------+-----------------------------------------------------+------+
++-----------------------------------------------------------------------------------------------+
+; Inverted Register Statistics ;
++-------------------------------------------------------------------------------------+---------+
+; Inverted Register ; Fan out ;
++-------------------------------------------------------------------------------------+---------+
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 1 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[1] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[4] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[5] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[7] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 2 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[8] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 2 ;
+; decode_stage:decode_st|dec_op_inst.condition[0] ; 1 ;
+; decode_stage:decode_st|dec_op_inst.condition[3] ; 1 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 2 ;
+; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 4 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[2] ; 13 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 1 ;
+; Total number of inverted registers = 26 ; ;
++-------------------------------------------------------------------------------------+---------+
+
+
++--------------------------------------------------------------------------------------------------------------------------+
+; Registers Packed Into Inferred Megafunctions ;
++------------------------------------------------------------+------------------------------------------------------+------+
+; Register Name ; Megafunction ; Type ;
++------------------------------------------------------------+------------------------------------------------------+------+
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[0] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[1] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[2] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[3] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[4] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[5] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[6] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[7] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[8] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[9] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[10] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[11] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[12] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[13] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[14] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[15] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[16] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[17] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[18] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[19] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[20] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[21] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[22] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[23] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[24] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[25] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[26] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[27] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[28] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[29] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[30] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|data_out[31] ; writeback_stage:writeback_st|r_w_ram:data_ram|ram~44 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out1[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~37 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[0] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[1] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[2] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[3] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[4] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[5] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[6] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[7] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[8] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[9] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[10] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[11] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[12] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[13] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[14] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[15] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[16] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[17] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[18] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[19] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[20] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[21] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[22] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[23] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[24] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[25] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[26] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[27] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[28] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[29] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[30] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
+; decode_stage:decode_st|r2_w_ram:register_ram|data_out2[31] ; decode_stage:decode_st|r2_w_ram:register_ram|ram~38 ; RAM ;
++------------------------------------------------------------+------------------------------------------------------+------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
-; 3:1 ; 21 bits ; 42 LEs ; 21 LEs ; 21 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25] ;
-; 3:1 ; 4 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |core_top|decode_stage:decode_st|dec_op_inst.displacement[1] ;
-; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ;
-; 5:1 ; 14 bits ; 42 LEs ; 28 LEs ; 14 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[31] ;
-; 5:1 ; 7 bits ; 21 LEs ; 14 LEs ; 7 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[19] ;
+; 3:1 ; 27 bits ; 54 LEs ; 27 LEs ; 27 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17] ;
+; 3:1 ; 6 bits ; 12 LEs ; 6 LEs ; 6 LEs ; Yes ; |core_top|decode_stage:decode_st|dec_op_inst.displacement[7] ;
+; 4:1 ; 18 bits ; 36 LEs ; 36 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|wb_reg.address[19] ;
+; 5:1 ; 21 bits ; 63 LEs ; 42 LEs ; 21 LEs ; Yes ; |core_top|fetch_stage:fetch_st|instr_r_addr[30] ;
; 18:1 ; 3 bits ; 36 LEs ; 3 LEs ; 33 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ;
-; 5:1 ; 32 bits ; 96 LEs ; 32 LEs ; 64 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[1] ;
-; 9:1 ; 5 bits ; 30 LEs ; 25 LEs ; 5 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[7] ;
-; 9:1 ; 13 bits ; 78 LEs ; 65 LEs ; 13 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[21] ;
-; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[4] ;
-; 10:1 ; 4 bits ; 24 LEs ; 24 LEs ; 0 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[25] ;
-; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[1] ;
-; 11:1 ; 2 bits ; 14 LEs ; 12 LEs ; 2 LEs ; Yes ; |core_top|execute_stage:exec_st|reg.result[29] ;
-; 3:1 ; 11 bits ; 22 LEs ; 22 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ;
+; 5:1 ; 16 bits ; 48 LEs ; 16 LEs ; 32 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4] ;
+; 3:1 ; 5 bits ; 10 LEs ; 10 LEs ; 0 LEs ; Yes ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ;
+; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |core_top|execute_stage:exec_st|condition[0] ;
+; 3:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.reg_src2_addr[1] ;
+; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|\split_instr:instr_s.op_group.JMP_ST_OP ;
+; 4:1 ; 4 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.immediate[8] ;
; 3:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|left_operand[19] ;
-; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
-; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[10] ;
-; 4:1 ; 26 bits ; 52 LEs ; 52 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[30] ;
-; 4:1 ; 30 bits ; 60 LEs ; 60 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector48 ;
-; 5:1 ; 5 bits ; 15 LEs ; 10 LEs ; 5 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[0] ;
-; 5:1 ; 6 bits ; 18 LEs ; 12 LEs ; 6 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[6] ;
-; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector97 ;
-; 6:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|Selector0 ;
-; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; No ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|Selector2 ;
+; 4:1 ; 32 bits ; 64 LEs ; 64 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|right_operand[5] ;
+; 4:1 ; 12 bits ; 24 LEs ; 24 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector63 ;
+; 5:1 ; 11 bits ; 33 LEs ; 22 LEs ; 11 LEs ; No ; |core_top|fetch_stage:fetch_st|instr_r_addr_nxt[0] ;
+; 4:1 ; 11 bits ; 22 LEs ; 11 LEs ; 11 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector98 ;
+; 32:1 ; 3 bits ; 63 LEs ; 6 LEs ; 57 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.reg_src1_addr[0] ;
+; 6:1 ; 9 bits ; 36 LEs ; 27 LEs ; 9 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
+; 7:1 ; 3 bits ; 12 LEs ; 6 LEs ; 6 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.immediate[12] ;
+; 10:1 ; 24 bits ; 144 LEs ; 96 LEs ; 48 LEs ; No ; |core_top|writeback_stage:writeback_st|regfile_val[24] ;
+; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_spl.immediate[3] ;
+; 11:1 ; 8 bits ; 56 LEs ; 48 LEs ; 8 LEs ; No ; |core_top|writeback_stage:writeback_st|regfile_val[0] ;
+; 10:1 ; 18 bits ; 108 LEs ; 108 LEs ; 0 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector16 ;
+; 11:1 ; 4 bits ; 28 LEs ; 24 LEs ; 4 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector3 ;
+; 11:1 ; 4 bits ; 28 LEs ; 24 LEs ; 4 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector28 ;
+; 12:1 ; 2 bits ; 16 LEs ; 14 LEs ; 2 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector1 ;
+; 12:1 ; 2 bits ; 16 LEs ; 14 LEs ; 2 LEs ; No ; |core_top|execute_stage:exec_st|alu:alu_inst|Selector29 ;
+; 14:1 ; 3 bits ; 27 LEs ; 21 LEs ; 6 LEs ; No ; |core_top|decode_stage:decode_st|decoder:decoder_inst|instr_s ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------------+
++--------------------------------------------------------------------------------------------------------------------------+
+; Source assignments for writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated ;
++---------------------------------+--------------------+------+------------------------------------------------------------+
+; Assignment ; Value ; From ; To ;
++---------------------------------+--------------------+------+------------------------------------------------------------+
+; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; - ; - ;
++---------------------------------+--------------------+------+------------------------------------------------------------+
+
+
+-------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ;
+; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
+-------------------------------------------------------------------------------------------------------------------------+
-; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ;
+; Source assignments for decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
; Assignment ; Value ; From ; To ;
+---------------------------------+--------------------+------+-----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-+-------------------------------------------------------------------------------------------+
-; Parameter Settings for User Entity Instance: fetch_stage:fetch_st|r_w_ram:instruction_ram ;
-+----------------+-------+------------------------------------------------------------------+
-; Parameter Name ; Value ; Type ;
-+----------------+-------+------------------------------------------------------------------+
-; addr_width ; 11 ; Signed Integer ;
-; data_width ; 32 ; Signed Integer ;
-+----------------+-------+------------------------------------------------------------------+
++---------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: fetch_stage:fetch_st|rom:instruction_ram ;
++----------------+-------+--------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+--------------------------------------------------------------+
+; addr_width ; 11 ; Signed Integer ;
+; data_width ; 32 ; Signed Integer ;
++----------------+-------+--------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
; Parameter Name ; Value ; Type ;
+----------------+-------+---------------------------------------------------------------------------------------------+
; reset_value ; '0' ; Enumerated ;
+; sync_stages ; 2 ; Signed Integer ;
+----------------+-------+---------------------------------------------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
++-----------------------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: writeback_stage:writeback_st|extension_7seg:sseg ;
++----------------+-------+----------------------------------------------------------------------+
+; Parameter Name ; Value ; Type ;
++----------------+-------+----------------------------------------------------------------------+
+; reset_value ; '0' ; Enumerated ;
++----------------+-------+----------------------------------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++---------------------------------------------------------------------------------------------------------------------+
+; Parameter Settings for Inferred Entity Instance: writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ;
++------------------------------------+-------------------------------------+------------------------------------------+
+; Parameter Name ; Value ; Type ;
++------------------------------------+-------------------------------------+------------------------------------------+
+; BYTE_SIZE_BLOCK ; 8 ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+; WIDTH_BYTEENA ; 1 ; Untyped ;
+; OPERATION_MODE ; DUAL_PORT ; Untyped ;
+; WIDTH_A ; 32 ; Untyped ;
+; WIDTHAD_A ; 11 ; Untyped ;
+; NUMWORDS_A ; 2048 ; Untyped ;
+; OUTDATA_REG_A ; UNREGISTERED ; Untyped ;
+; ADDRESS_ACLR_A ; NONE ; Untyped ;
+; OUTDATA_ACLR_A ; NONE ; Untyped ;
+; WRCONTROL_ACLR_A ; NONE ; Untyped ;
+; INDATA_ACLR_A ; NONE ; Untyped ;
+; BYTEENA_ACLR_A ; NONE ; Untyped ;
+; WIDTH_B ; 32 ; Untyped ;
+; WIDTHAD_B ; 11 ; Untyped ;
+; NUMWORDS_B ; 2048 ; Untyped ;
+; INDATA_REG_B ; CLOCK1 ; Untyped ;
+; WRCONTROL_WRADDRESS_REG_B ; CLOCK1 ; Untyped ;
+; RDCONTROL_REG_B ; CLOCK1 ; Untyped ;
+; ADDRESS_REG_B ; CLOCK0 ; Untyped ;
+; OUTDATA_REG_B ; UNREGISTERED ; Untyped ;
+; BYTEENA_REG_B ; CLOCK1 ; Untyped ;
+; INDATA_ACLR_B ; NONE ; Untyped ;
+; WRCONTROL_ACLR_B ; NONE ; Untyped ;
+; ADDRESS_ACLR_B ; NONE ; Untyped ;
+; OUTDATA_ACLR_B ; NONE ; Untyped ;
+; RDCONTROL_ACLR_B ; NONE ; Untyped ;
+; BYTEENA_ACLR_B ; NONE ; Untyped ;
+; WIDTH_BYTEENA_A ; 1 ; Untyped ;
+; WIDTH_BYTEENA_B ; 1 ; Untyped ;
+; RAM_BLOCK_TYPE ; AUTO ; Untyped ;
+; BYTE_SIZE ; 8 ; Untyped ;
+; READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ; Untyped ;
+; READ_DURING_WRITE_MODE_PORT_A ; NEW_DATA_NO_NBE_READ ; Untyped ;
+; READ_DURING_WRITE_MODE_PORT_B ; NEW_DATA_NO_NBE_READ ; Untyped ;
+; INIT_FILE ; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ; Untyped ;
+; INIT_FILE_LAYOUT ; PORT_A ; Untyped ;
+; MAXIMUM_DEPTH ; 0 ; Untyped ;
+; CLOCK_ENABLE_INPUT_A ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_INPUT_B ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_OUTPUT_A ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_OUTPUT_B ; NORMAL ; Untyped ;
+; CLOCK_ENABLE_CORE_A ; USE_INPUT_CLKEN ; Untyped ;
+; CLOCK_ENABLE_CORE_B ; USE_INPUT_CLKEN ; Untyped ;
+; ENABLE_ECC ; FALSE ; Untyped ;
+; DEVICE_FAMILY ; Cyclone ; Untyped ;
+; CBXI_PARAMETER ; altsyncram_grk1 ; Untyped ;
++------------------------------------+-------------------------------------+------------------------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
+--------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ;
+; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
+------------------------------------+--------------------------------------+----------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+--------------------------------------+----------------------------------------+
+--------------------------------------------------------------------------------------------------------------------+
-; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
+; Parameter Settings for Inferred Entity Instance: decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ;
+------------------------------------+--------------------------------------+----------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------------------+--------------------------------------+----------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
-+---------------------------------------------------------------------------------------------------------------+
-; altsyncram Parameter Settings by Entity Instance ;
-+-------------------------------------------+-------------------------------------------------------------------+
-; Name ; Value ;
-+-------------------------------------------+-------------------------------------------------------------------+
-; Number of entity instances ; 2 ;
-; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ;
-; -- OPERATION_MODE ; DUAL_PORT ;
-; -- WIDTH_A ; 32 ;
-; -- NUMWORDS_A ; 16 ;
-; -- OUTDATA_REG_A ; UNREGISTERED ;
-; -- WIDTH_B ; 32 ;
-; -- NUMWORDS_B ; 16 ;
-; -- ADDRESS_REG_B ; CLOCK0 ;
-; -- OUTDATA_REG_B ; UNREGISTERED ;
-; -- RAM_BLOCK_TYPE ; AUTO ;
-; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
-; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
-; -- OPERATION_MODE ; DUAL_PORT ;
-; -- WIDTH_A ; 32 ;
-; -- NUMWORDS_A ; 16 ;
-; -- OUTDATA_REG_A ; UNREGISTERED ;
-; -- WIDTH_B ; 32 ;
-; -- NUMWORDS_B ; 16 ;
-; -- ADDRESS_REG_B ; CLOCK0 ;
-; -- OUTDATA_REG_B ; UNREGISTERED ;
-; -- RAM_BLOCK_TYPE ; AUTO ;
-; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
-+-------------------------------------------+-------------------------------------------------------------------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst" ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-; new_rx_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-; rx_data ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+-------------+--------+----------+-------------------------------------------------------------------------------------+
-
-
-+--------------------------------------------------------------------------------------------------------------------+
-; Port Connectivity Checks: "writeback_stage:writeback_st|extension_uart:uart" ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-; Port ; Type ; Severity ; Details ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
-; data_out ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
-+----------+--------+----------+-------------------------------------------------------------------------------------+
++----------------------------------------------------------------------------------------------------------------+
+; altsyncram Parameter Settings by Entity Instance ;
++-------------------------------------------+--------------------------------------------------------------------+
+; Name ; Value ;
++-------------------------------------------+--------------------------------------------------------------------+
+; Number of entity instances ; 3 ;
+; Entity Instance ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ;
+; -- OPERATION_MODE ; DUAL_PORT ;
+; -- WIDTH_A ; 32 ;
+; -- NUMWORDS_A ; 2048 ;
+; -- OUTDATA_REG_A ; UNREGISTERED ;
+; -- WIDTH_B ; 32 ;
+; -- NUMWORDS_B ; 2048 ;
+; -- ADDRESS_REG_B ; CLOCK0 ;
+; -- OUTDATA_REG_B ; UNREGISTERED ;
+; -- RAM_BLOCK_TYPE ; AUTO ;
+; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
+; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ;
+; -- OPERATION_MODE ; DUAL_PORT ;
+; -- WIDTH_A ; 32 ;
+; -- NUMWORDS_A ; 16 ;
+; -- OUTDATA_REG_A ; UNREGISTERED ;
+; -- WIDTH_B ; 32 ;
+; -- NUMWORDS_B ; 16 ;
+; -- ADDRESS_REG_B ; CLOCK0 ;
+; -- OUTDATA_REG_B ; UNREGISTERED ;
+; -- RAM_BLOCK_TYPE ; AUTO ;
+; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
+; Entity Instance ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ;
+; -- OPERATION_MODE ; DUAL_PORT ;
+; -- WIDTH_A ; 32 ;
+; -- NUMWORDS_A ; 16 ;
+; -- OUTDATA_REG_A ; UNREGISTERED ;
+; -- WIDTH_B ; 32 ;
+; -- NUMWORDS_B ; 16 ;
+; -- ADDRESS_REG_B ; CLOCK0 ;
+; -- OUTDATA_REG_B ; UNREGISTERED ;
+; -- RAM_BLOCK_TYPE ; AUTO ;
+; -- READ_DURING_WRITE_MODE_MIXED_PORTS ; OLD_DATA ;
++-------------------------------------------+--------------------------------------------------------------------+
+----------------------------------------------------------------------------------------------------------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 12:26:25 2010
+ Info: Processing started: Sun Dec 19 20:36:12 2010
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dt -c dt
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/rs232_rx_arc.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rom.vhd
+ Info: Found entity 1: rom
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rom_b.vhd
+ Info: Found design unit 1: rom-behaviour
+Info: Found 2 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_7seg_pkg.vhd
+ Info: Found design unit 1: extension_7seg_pkg
+ Info: Found design unit 2: extension_7seg_pkg-body
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_7seg_b.vhd
+ Info: Found design unit 1: extension_7seg-behav
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/extension_7seg.vhd
+ Info: Found entity 1: extension_7seg
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_rx_arc.vhd
Info: Found design unit 1: rs232_rx-beh
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/rs232_rx.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_rx.vhd
Info: Found entity 1: rs232_rx
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/writeback_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/writeback_stage_b.vhd
Info: Found design unit 1: writeback_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/writeback_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/writeback_stage.vhd
Info: Found entity 1: writeback_stage
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/rw_r_ram_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rw_r_ram_b.vhd
Info: Found design unit 1: rw_r_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/rw_r_ram.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rw_r_ram.vhd
Info: Found entity 1: rw_r_ram
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/rs232_tx_arc.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_tx_arc.vhd
Info: Found design unit 1: rs232_tx-beh
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/rs232_tx.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/rs232_tx.vhd
Info: Found entity 1: rs232_tx
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/r_w_ram_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/r_w_ram_b.vhd
Info: Found design unit 1: r_w_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/r_w_ram.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/r_w_ram.vhd
Info: Found entity 1: r_w_ram
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/r2_w_ram_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/r2_w_ram_b.vhd
Info: Found design unit 1: r2_w_ram-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/r2_w_ram.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/r2_w_ram.vhd
Info: Found entity 1: r2_w_ram
-Info: Found 3 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/pipeline_tb.vhd
+Info: Found 3 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/pipeline_tb.vhd
Info: Found design unit 1: pipeline_tb-behavior
Info: Found design unit 2: pipeline_conf_beh
Info: Found entity 1: pipeline_tb
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/mem_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/mem_pkg.vhd
Info: Found design unit 1: mem_pkg
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/fetch_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/fetch_stage_b.vhd
Info: Found design unit 1: fetch_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/fetch_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/fetch_stage.vhd
Info: Found entity 1: fetch_stage
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_uart_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_uart_pkg.vhd
Info: Found design unit 1: extension_uart_pkg
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_uart_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_uart_b.vhd
Info: Found design unit 1: extension_uart-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/extension_uart.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/extension_uart.vhd
Info: Found entity 1: extension_uart
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_pkg.vhd
Info: Found design unit 1: extension_pkg
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/extension_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/extension_b.vhd
Info: Found design unit 1: extension_gpm-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/extension.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/extension.vhd
Info: Found entity 1: extension_gpm
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/execute_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/execute_stage_b.vhd
Info: Found design unit 1: execute_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/execute_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/execute_stage.vhd
Info: Found entity 1: execute_stage
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/exec_op.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op.vhd
Info: Found entity 1: exec_op
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/decoder_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/decoder_b.vhd
Info: Found design unit 1: decoder-behav_d
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/decoder.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/decoder.vhd
Info: Found entity 1: decoder
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/decode_stage_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/decode_stage_b.vhd
Info: Found design unit 1: decode_stage-behav
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/decode_stage.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/decode_stage.vhd
Info: Found entity 1: decode_stage
-Info: Found 2 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/core_top.vhd
+Info: Found 2 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/core_top.vhd
Info: Found design unit 1: core_top-behav
Info: Found entity 1: core_top
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/core_pkg.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/core_pkg.vhd
Info: Found design unit 1: core_pkg
-Info: Found 2 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/common_pkg.vhd
+Info: Found 2 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/common_pkg.vhd
Info: Found design unit 1: common_pkg
Info: Found design unit 2: common_pkg-body
-Info: Found 2 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/alu_pkg.vhd
+Info: Found 2 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/alu_pkg.vhd
Info: Found design unit 1: alu_pkg
Info: Found design unit 2: alu_pkg-body
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/alu_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/alu_b.vhd
Info: Found design unit 1: alu-behaviour
-Info: Found 1 design units, including 1 entities, in source file /homes/c0726283/calu/cpu/src/alu.vhd
+Info: Found 1 design units, including 1 entities, in source file /home/stefan/processor/calu/cpu/src/alu.vhd
Info: Found entity 1: alu
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/xor_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/xor_op_b.vhd
Info: Found design unit 1: exec_op-xor_op
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/shift_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/shift_op_b.vhd
Info: Found design unit 1: exec_op-shift_op
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/or_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/or_op_b.vhd
Info: Found design unit 1: exec_op-or_op
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/and_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/and_op_b.vhd
Info: Found design unit 1: exec_op-and_op
-Info: Found 1 design units, including 0 entities, in source file /homes/c0726283/calu/cpu/src/exec_op/add_op_b.vhd
+Info: Found 1 design units, including 0 entities, in source file /home/stefan/processor/calu/cpu/src/exec_op/add_op_b.vhd
Info: Found design unit 1: exec_op-add_op
Info: Elaborating entity "core_top" for the top level hierarchy
-Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(25): object "jump_result" assigned a value but never read
-Warning (10541): VHDL Signal Declaration warning at core_top.vhd(53): used implicit default value for signal "gpm_in_pin" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
-Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(54): object "gpm_out_pin" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(31): object "jump_result" assigned a value but never read
+Warning (10541): VHDL Signal Declaration warning at core_top.vhd(59): used implicit default value for signal "gpm_in_pin" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
+Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(60): object "gpm_out_pin" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at core_top.vhd(63): object "vers" assigned a value but never read
Info: Elaborating entity "fetch_stage" for hierarchy "fetch_stage:fetch_st"
Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(11): used implicit default value for signal "instr_w_addr" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(14): used implicit default value for signal "instr_we" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
Warning (10541): VHDL Signal Declaration warning at fetch_stage_b.vhd(15): used implicit default value for signal "instr_wr_data" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
-Info: Elaborating entity "r_w_ram" for hierarchy "fetch_stage:fetch_st|r_w_ram:instruction_ram"
-Warning (10036): Verilog HDL or VHDL warning at r_w_ram_b.vhd(15): object "ram" assigned a value but never read
+Info: Elaborating entity "rom" for hierarchy "fetch_stage:fetch_st|rom:instruction_ram"
Info: Elaborating entity "decode_stage" for hierarchy "decode_stage:decode_st"
Info: Elaborating entity "r2_w_ram" for hierarchy "decode_stage:decode_st|r2_w_ram:register_ram"
Info: Elaborating entity "decoder" for hierarchy "decode_stage:decode_st|decoder:decoder_inst"
Info: Elaborating entity "exec_op" using architecture "A:shift_op" for hierarchy "execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst"
Info: Elaborating entity "extension_gpm" for hierarchy "execute_stage:exec_st|extension_gpm:gpmp_inst"
Info: Elaborating entity "writeback_stage" for hierarchy "writeback_stage:writeback_st"
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(14): object "data_ram_read_ext" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(19): object "ext_timer" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(19): object "ext_gpmp" assigned a value but never read
-Warning (10812): VHDL warning at writeback_stage_b.vhd(164): sensitivity list already contains wb_reg_nxt
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(20): object "ext_timer" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(20): object "ext_gpmp" assigned a value but never read
+Warning (10036): Verilog HDL or VHDL warning at writeback_stage_b.vhd(25): object "calc_mem_res" assigned a value but never read
+Info: Elaborating entity "r_w_ram" for hierarchy "writeback_stage:writeback_st|r_w_ram:data_ram"
Info: Elaborating entity "extension_uart" for hierarchy "writeback_stage:writeback_st|extension_uart:uart"
-Warning (10036): Verilog HDL or VHDL warning at extension_uart_b.vhd(15): object "new_bus_rx" assigned a value but never read
-Warning (10036): Verilog HDL or VHDL warning at extension_uart_b.vhd(17): object "rx_data" assigned a value but never read
Info: Elaborating entity "rs232_tx" for hierarchy "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst"
Info: Elaborating entity "rs232_rx" for hierarchy "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst"
-Info: Inferred 2 megafunctions from design logic
+Info: Elaborating entity "extension_7seg" for hierarchy "writeback_stage:writeback_st|extension_7seg:sseg"
+Info: Inferred 3 megafunctions from design logic
+ Info: Inferred altsyncram megafunction from the following design logic: "writeback_stage:writeback_st|r_w_ram:data_ram|ram~44"
+ Info: Parameter OPERATION_MODE set to DUAL_PORT
+ Info: Parameter WIDTH_A set to 32
+ Info: Parameter WIDTHAD_A set to 11
+ Info: Parameter NUMWORDS_A set to 2048
+ Info: Parameter WIDTH_B set to 32
+ Info: Parameter WIDTHAD_B set to 11
+ Info: Parameter NUMWORDS_B set to 2048
+ Info: Parameter ADDRESS_ACLR_A set to NONE
+ Info: Parameter OUTDATA_REG_B set to UNREGISTERED
+ Info: Parameter ADDRESS_ACLR_B set to NONE
+ Info: Parameter OUTDATA_ACLR_B set to NONE
+ Info: Parameter ADDRESS_REG_B set to CLOCK0
+ Info: Parameter INDATA_ACLR_A set to NONE
+ Info: Parameter WRCONTROL_ACLR_A set to NONE
+ Info: Parameter INIT_FILE set to db/dt.ram0_r_w_ram_1e9198d1.hdl.mif
+ Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
Info: Inferred altsyncram megafunction from the following design logic: "decode_stage:decode_st|r2_w_ram:register_ram|ram~37"
Info: Parameter OPERATION_MODE set to DUAL_PORT
Info: Parameter WIDTH_A set to 32
Info: Parameter WRCONTROL_ACLR_A set to NONE
Info: Parameter INIT_FILE set to db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif
Info: Parameter READ_DURING_WRITE_MODE_MIXED_PORTS set to OLD_DATA
-Info: Elaborated megafunction instantiation "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0"
-Info: Instantiated megafunction "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0" with the following parameter:
+Info: Elaborated megafunction instantiation "writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0"
+Info: Instantiated megafunction "writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0" with the following parameter:
Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
Info: Parameter "WIDTH_A" = "32"
- Info: Parameter "WIDTHAD_A" = "4"
- Info: Parameter "NUMWORDS_A" = "16"
+ Info: Parameter "WIDTHAD_A" = "11"
+ Info: Parameter "NUMWORDS_A" = "2048"
Info: Parameter "WIDTH_B" = "32"
- Info: Parameter "WIDTHAD_B" = "4"
- Info: Parameter "NUMWORDS_B" = "16"
+ Info: Parameter "WIDTHAD_B" = "11"
+ Info: Parameter "NUMWORDS_B" = "2048"
Info: Parameter "ADDRESS_ACLR_A" = "NONE"
Info: Parameter "OUTDATA_REG_B" = "UNREGISTERED"
Info: Parameter "ADDRESS_ACLR_B" = "NONE"
Info: Parameter "ADDRESS_REG_B" = "CLOCK0"
Info: Parameter "INDATA_ACLR_A" = "NONE"
Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
- Info: Parameter "INIT_FILE" = "db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif"
+ Info: Parameter "INIT_FILE" = "db/dt.ram0_r_w_ram_1e9198d1.hdl.mif"
Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
-Info: Found 1 design units, including 1 entities, in source file db/altsyncram_emk1.tdf
- Info: Found entity 1: altsyncram_emk1
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_grk1.tdf
+ Info: Found entity 1: altsyncram_grk1
Info: Elaborated megafunction instantiation "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1"
Info: Instantiated megafunction "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1" with the following parameter:
Info: Parameter "OPERATION_MODE" = "DUAL_PORT"
Info: Parameter "WRCONTROL_ACLR_A" = "NONE"
Info: Parameter "INIT_FILE" = "db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif"
Info: Parameter "READ_DURING_WRITE_MODE_MIXED_PORTS" = "OLD_DATA"
+Info: Found 1 design units, including 1 entities, in source file db/altsyncram_emk1.tdf
+ Info: Found entity 1: altsyncram_emk1
Info: Registers with preset signals will power-up high
-Info: 187 registers lost all their fanouts during netlist optimizations. The first 187 are displayed below.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo" lost all its fanouts during netlist optimizations.
- Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign" lost all its fanouts during netlist optimizations.
+Info: 130 registers lost all their fanouts during netlist optimizations. The first 130 are displayed below.
+ Info: Register "writeback_stage:writeback_st|wb_reg.address[0]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|wb_reg.address[1]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][29]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][28]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[1][27]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][2]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][1]" lost all its fanouts during netlist optimizations.
Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[3][0]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.daddr[2]" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.op_group.AND_OP" lost all its fanouts during netlist optimizations.
- Info: Register "decode_stage:decode_st|dec_op_inst.op_group.XOR_OP" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[31]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[30]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[29]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[28]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[27]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[26]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[25]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[24]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[23]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[22]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[21]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[20]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[19]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[18]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[17]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[16]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[15]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[14]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[13]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[12]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[11]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[10]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[9]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[8]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[7]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[6]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[5]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[3]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[2]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[1]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[0]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[30]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[29]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[28]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[27]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[26]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[25]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[24]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[23]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[22]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[21]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[20]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[19]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[18]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[17]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[16]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[15]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[14]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[13]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[12]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[11]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0]" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.IDLE" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP" lost all its fanouts during netlist optimizations.
- Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.POST_STOP" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo" lost all its fanouts during netlist optimizations.
+ Info: Register "execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.sign" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[11]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[12]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[13]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[29]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[30]" lost all its fanouts during netlist optimizations.
Info: Register "fetch_stage:fetch_st|instr_r_addr[31]" lost all its fanouts during netlist optimizations.
-Info: Removed 1 MSB VCC or GND address nodes from RAM block "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM"
-Info: Removed 1 MSB VCC or GND address nodes from RAM block "decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM"
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[31]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[30]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[29]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[28]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[27]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[26]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[24]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[18]" lost all its fanouts during netlist optimizations.
+ Info: Register "writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17]" lost all its fanouts during netlist optimizations.
Info: Generating hard_block partition "hard_block:auto_generated_inst"
-Info: Implemented 1210 device resources after synthesis - the final resource count might be different
- Info: Implemented 2 input pins
- Info: Implemented 1 output pins
- Info: Implemented 1143 logic cells
- Info: Implemented 64 RAM segments
-Info: Quartus II Analysis & Synthesis was successful. 0 errors, 14 warnings
- Info: Peak virtual memory: 268 megabytes
- Info: Processing ended: Fri Dec 17 12:26:49 2010
- Info: Elapsed time: 00:00:24
- Info: Total CPU time (on all processors): 00:00:22
+Info: Implemented 2007 device resources after synthesis - the final resource count might be different
+ Info: Implemented 3 input pins
+ Info: Implemented 29 output pins
+ Info: Implemented 1879 logic cells
+ Info: Implemented 96 RAM segments
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
+ Info: Peak virtual memory: 270 megabytes
+ Info: Processing ended: Sun Dec 19 20:36:26 2010
+ Info: Elapsed time: 00:00:14
+ Info: Total CPU time (on all processors): 00:00:13
projects / calu.git / blobdiff