Fitter report for dt
-Fri Dec 17 12:27:10 2010
+Sun Dec 19 20:36:44 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+-----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------------+
-; Fitter Status ; Successful - Fri Dec 17 12:27:10 2010 ;
+; Fitter Status ; Successful - Sun Dec 19 20:36:44 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
; Device ; EP1C12Q240C8 ;
; Timing Models ; Final ;
-; Total logic elements ; 1,058 / 12,060 ( 9 % ) ;
-; Total pins ; 3 / 173 ( 2 % ) ;
+; Total logic elements ; 1,646 / 12,060 ( 14 % ) ;
+; Total pins ; 32 / 173 ( 18 % ) ;
; Total virtual pins ; 0 ;
-; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
+; Total memory bits ; 66,560 / 239,616 ( 28 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+-----------------------+-----------------------------------------------+
; Type ; Value ;
+---------------------+------------------------+
; Placement (by node) ; ;
-; -- Requested ; 0 / 1127 ( 0.00 % ) ;
-; -- Achieved ; 0 / 1127 ( 0.00 % ) ;
+; -- Requested ; 0 / 1777 ( 0.00 % ) ;
+; -- Achieved ; 0 / 1777 ( 0.00 % ) ;
; ; ;
; Routing (by net) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
-; Top ; 1125 ; 0 ; N/A ; Source File ;
+; Top ; 1775 ; 0 ; N/A ; Source File ;
; hard_block:auto_generated_inst ; 2 ; 0 ; N/A ; Source File ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
+--------------+
; Pin-Out File ;
+--------------+
-The pin-out file can be found in /homes/c0726283/calu/dt/dt.pin.
-
-
-+-----------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+-------------------------------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+-------------------------------------------------+
-; Total logic elements ; 1,058 / 12,060 ( 9 % ) ;
-; -- Combinational with no register ; 843 ;
-; -- Register only ; 0 ;
-; -- Combinational with a register ; 215 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 473 ;
-; -- 3 input functions ; 443 ;
-; -- 2 input functions ; 123 ;
-; -- 1 input functions ; 18 ;
-; -- 0 input functions ; 1 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 852 ;
-; -- arithmetic mode ; 206 ;
-; -- qfbk mode ; 76 ;
-; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 83 ;
-; -- asynchronous clear/load mode ; 203 ;
-; ; ;
-; Total registers ; 215 / 12,567 ( 2 % ) ;
-; Total LABs ; 111 / 1,206 ( 9 % ) ;
-; Logic elements in carry chains ; 214 ;
-; User inserted logic elements ; 0 ;
-; Virtual pins ; 0 ;
-; I/O pins ; 3 / 173 ( 2 % ) ;
-; -- Clock pins ; 1 / 2 ( 50 % ) ;
-; Global signals ; 2 ;
-; M4Ks ; 2 / 52 ( 4 % ) ;
-; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
-; Total RAM block bits ; 9,216 / 239,616 ( 4 % ) ;
-; PLLs ; 0 / 2 ( 0 % ) ;
-; Global clocks ; 2 / 8 ( 25 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; ASMI Blocks ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 5% / 5% / 4% ;
-; Peak interconnect usage (total/H/V) ; 17% / 19% / 14% ;
-; Maximum fan-out node ; sys_clk ;
-; Maximum fan-out ; 217 ;
-; Highest non-global fan-out signal ; execute_stage:exec_st|alu:alu_inst|Selector76~0 ;
-; Highest non-global fan-out ; 114 ;
-; Total fan-out ; 4182 ;
-; Average fan-out ; 3.93 ;
-+---------------------------------------------+-------------------------------------------------+
+The pin-out file can be found in /home/stefan/processor/calu/dt/dt.pin.
+
+
++-----------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+-------------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+-------------------------------------------+
+; Total logic elements ; 1,646 / 12,060 ( 14 % ) ;
+; -- Combinational with no register ; 1126 ;
+; -- Register only ; 26 ;
+; -- Combinational with a register ; 494 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 827 ;
+; -- 3 input functions ; 474 ;
+; -- 2 input functions ; 292 ;
+; -- 1 input functions ; 27 ;
+; -- 0 input functions ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 1470 ;
+; -- arithmetic mode ; 176 ;
+; -- qfbk mode ; 179 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 246 ;
+; -- asynchronous clear/load mode ; 492 ;
+; ; ;
+; Total registers ; 520 / 12,567 ( 4 % ) ;
+; Total LABs ; 174 / 1,206 ( 14 % ) ;
+; Logic elements in carry chains ; 184 ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 32 / 173 ( 18 % ) ;
+; -- Clock pins ; 1 / 2 ( 50 % ) ;
+; Global signals ; 2 ;
+; M4Ks ; 18 / 52 ( 35 % ) ;
+; Total memory bits ; 66,560 / 239,616 ( 28 % ) ;
+; Total RAM block bits ; 82,944 / 239,616 ( 35 % ) ;
+; PLLs ; 0 / 2 ( 0 % ) ;
+; Global clocks ; 2 / 8 ( 25 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI Blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 12% / 12% / 11% ;
+; Peak interconnect usage (total/H/V) ; 42% / 44% / 40% ;
+; Maximum fan-out node ; sys_clk ;
+; Maximum fan-out ; 538 ;
+; Highest non-global fan-out signal ; execute_stage:exec_st|right_operand[0]~19 ;
+; Highest non-global fan-out ; 104 ;
+; Total fan-out ; 7140 ;
+; Average fan-out ; 4.20 ;
++---------------------------------------------+-------------------------------------------+
+---------------------------------------------------------------------------------------------------+
+---------------------------------------------+--------------------+--------------------------------+
; Difficulty Clustering Region ; Low ; Low ;
; ; ; ;
-; Total logic elements ; 1058 ; 0 ;
-; -- Combinational with no register ; 843 ; 0 ;
-; -- Register only ; 0 ; 0 ;
-; -- Combinational with a register ; 215 ; 0 ;
+; Total logic elements ; 1646 ; 0 ;
+; -- Combinational with no register ; 1126 ; 0 ;
+; -- Register only ; 26 ; 0 ;
+; -- Combinational with a register ; 494 ; 0 ;
; ; ; ;
; Logic element usage by number of LUT inputs ; ; ;
; -- 4 input functions ; 0 ; 0 ;
; -- synchronous clear/load mode ; 0 ; 0 ;
; -- asynchronous clear/load mode ; 0 ; 0 ;
; ; ; ;
-; Total registers ; 215 / 6030 ( 3 % ) ; 0 / 6030 ( 0 % ) ;
+; Total registers ; 520 / 6030 ( 8 % ) ; 0 / 6030 ( 0 % ) ;
; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 3 ; 0 ;
+; I/O pins ; 32 ; 0 ;
; DSP block 9-bit elements ; 0 ; 0 ;
-; Total memory bits ; 512 ; 0 ;
-; Total RAM block bits ; 9216 ; 0 ;
-; M4K ; 2 / 52 ( 3 % ) ; 0 / 52 ( 0 % ) ;
+; Total memory bits ; 66560 ; 0 ;
+; Total RAM block bits ; 82944 ; 0 ;
+; M4K ; 18 / 52 ( 34 % ) ; 0 / 52 ( 0 % ) ;
; ; ; ;
; Connections ; ; ;
; -- Input Connections ; 0 ; 0 ;
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
-; -- Total Connections ; 4355 ; 0 ;
-; -- Registered Connections ; 809 ; 0 ;
+; -- Total Connections ; 7455 ; 0 ;
+; -- Registered Connections ; 1762 ; 0 ;
; ; ; ;
; External Connections ; ; ;
; -- Top ; 0 ; 0 ;
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
; ; ; ;
; Partition Interface ; ; ;
-; -- Input Ports ; 2 ; 0 ;
-; -- Output Ports ; 1 ; 0 ;
+; -- Input Ports ; 3 ; 0 ;
+; -- Output Ports ; 29 ; 0 ;
; -- Bidir Ports ; 0 ; 0 ;
; ; ; ;
; Registered Ports ; ; ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; sys_clk ; 152 ; 3 ; 53 ; 15 ; 2 ; 217 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
-; sys_res ; 42 ; 1 ; 0 ; 6 ; 0 ; 205 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+; bus_rx ; 17 ; 1 ; 0 ; 21 ; 0 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; Fitter ;
+; sys_clk ; 152 ; 3 ; 53 ; 15 ; 2 ; 538 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+; sys_res ; 42 ; 1 ; 0 ; 6 ; 0 ; 504 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Output Pins ;
-+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
-; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
-+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
-; bus_tx ; 166 ; 3 ; 53 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 10 pF ; - ; - ;
-+--------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Output Pins ;
++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
+; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; Slow Slew Rate ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ;
++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
+; bus_tx ; 166 ; 3 ; 53 ; 22 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; User ; 10 pF ; - ; - ;
+; sseg0[0] ; 83 ; 4 ; 14 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[1] ; 86 ; 4 ; 16 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[2] ; 144 ; 3 ; 53 ; 12 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[3] ; 39 ; 1 ; 0 ; 11 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[4] ; 213 ; 2 ; 18 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[5] ; 88 ; 4 ; 18 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg0[6] ; 214 ; 2 ; 16 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[0] ; 18 ; 1 ; 0 ; 21 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[1] ; 93 ; 4 ; 26 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[2] ; 94 ; 4 ; 28 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[3] ; 162 ; 3 ; 53 ; 21 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[4] ; 207 ; 2 ; 28 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[5] ; 206 ; 2 ; 28 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg1[6] ; 95 ; 4 ; 28 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[0] ; 21 ; 1 ; 0 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[1] ; 201 ; 2 ; 32 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[2] ; 161 ; 3 ; 53 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[3] ; 202 ; 2 ; 32 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[4] ; 20 ; 1 ; 0 ; 20 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[5] ; 200 ; 2 ; 32 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg2[6] ; 160 ; 3 ; 53 ; 20 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[0] ; 87 ; 4 ; 16 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[1] ; 84 ; 4 ; 14 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[2] ; 38 ; 1 ; 0 ; 11 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[3] ; 23 ; 1 ; 0 ; 16 ; 0 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[4] ; 85 ; 4 ; 16 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[5] ; 215 ; 2 ; 16 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
+; sseg3[6] ; 216 ; 2 ; 16 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; 12mA ; Off ; Fitter ; 10 pF ; - ; - ;
++----------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+----------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+-------+----------------------+---------------------+
-+----------------------------------------------------------+
-; I/O Bank Usage ;
-+----------+----------------+---------------+--------------+
-; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
-+----------+----------------+---------------+--------------+
-; 1 ; 3 / 44 ( 7 % ) ; 3.3V ; -- ;
-; 2 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ;
-; 3 ; 2 / 45 ( 4 % ) ; 3.3V ; -- ;
-; 4 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ;
-+----------+----------------+---------------+--------------+
++------------------------------------------------------------+
+; I/O Bank Usage ;
++----------+------------------+---------------+--------------+
+; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
++----------+------------------+---------------+--------------+
+; 1 ; 10 / 44 ( 23 % ) ; 3.3V ; -- ;
+; 2 ; 9 / 42 ( 21 % ) ; 3.3V ; -- ;
+; 3 ; 6 / 45 ( 13 % ) ; 3.3V ; -- ;
+; 4 ; 9 / 42 ( 21 % ) ; 3.3V ; -- ;
++----------+------------------+---------------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 14 ; 11 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 15 ; 12 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 16 ; 13 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 17 ; 14 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 18 ; 15 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 17 ; 14 ; 1 ; bus_rx ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
+; 18 ; 15 ; 1 ; sseg1[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 19 ; 16 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 20 ; 17 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 21 ; 18 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 20 ; 17 ; 1 ; sseg2[4] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
+; 21 ; 18 ; 1 ; sseg2[0] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 22 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 23 ; 28 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 23 ; 28 ; 1 ; sseg3[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 24 ; 29 ; 1 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; On ;
; 25 ; 30 ; 1 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ;
; 26 ; 31 ; 1 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ;
; 35 ; 37 ; 1 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ;
; 36 ; 38 ; 1 ; ^DCLK ; bidir ; ; ; -- ; ; -- ; -- ;
; 37 ; 39 ; 1 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; On ;
-; 38 ; 40 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 39 ; 41 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 38 ; 40 ; 1 ; sseg3[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
+; 39 ; 41 ; 1 ; sseg0[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 40 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 41 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 42 ; 53 ; 1 ; sys_res ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 80 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 81 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 82 ; 86 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 83 ; 87 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 84 ; 88 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 85 ; 89 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 86 ; 90 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 87 ; 91 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 88 ; 92 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 83 ; 87 ; 4 ; sseg0[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 84 ; 88 ; 4 ; sseg3[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 85 ; 89 ; 4 ; sseg3[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 86 ; 90 ; 4 ; sseg0[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 87 ; 91 ; 4 ; sseg3[0] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 88 ; 92 ; 4 ; sseg0[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
; 89 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 90 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 91 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 92 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
-; 93 ; 100 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 94 ; 103 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 95 ; 104 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 93 ; 100 ; 4 ; sseg1[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 94 ; 103 ; 4 ; sseg1[2] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 95 ; 104 ; 4 ; sseg1[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
; 96 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 97 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 98 ; 106 ; 4 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 141 ; 149 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 142 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 143 ; 160 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 144 ; 161 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 144 ; 161 ; 3 ; sseg0[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 145 ; 162 ; 3 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ;
; 146 ; 163 ; 3 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ;
; 147 ; 164 ; 3 ; #TCK ; input ; ; ; -- ; ; -- ; -- ;
; 157 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 158 ; 180 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 159 ; 181 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 160 ; 182 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 161 ; 183 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 162 ; 184 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 160 ; 182 ; 3 ; sseg2[6] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
+; 161 ; 183 ; 3 ; sseg2[2] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
+; 162 ; 184 ; 3 ; sseg1[3] ; output ; 3.3-V LVCMOS ; ; Row I/O ; N ; no ; Off ;
; 163 ; 185 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 164 ; 186 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 165 ; 187 ; 3 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 197 ; 213 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 198 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 199 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 200 ; 222 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 201 ; 223 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 202 ; 224 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 200 ; 222 ; 2 ; sseg2[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 201 ; 223 ; 2 ; sseg2[1] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 202 ; 224 ; 2 ; sseg2[3] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
; 203 ; 225 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 204 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 205 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 206 ; 227 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 207 ; 228 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 206 ; 227 ; 2 ; sseg1[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 207 ; 228 ; 2 ; sseg1[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
; 208 ; 231 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 209 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ;
; 210 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 211 ; ; ; VCCINT ; power ; ; 1.5V ; -- ; ; -- ; -- ;
; 212 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
-; 213 ; 239 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 214 ; 240 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 215 ; 241 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
-; 216 ; 242 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
+; 213 ; 239 ; 2 ; sseg0[4] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 214 ; 240 ; 2 ; sseg0[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 215 ; 241 ; 2 ; sseg3[5] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
+; 216 ; 242 ; 2 ; sseg3[6] ; output ; 3.3-V LVCMOS ; ; Column I/O ; N ; no ; Off ;
; 217 ; 243 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 218 ; 244 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
; 219 ; 245 ; 2 ; RESERVED_INPUT ; ; ; ; Column I/O ; ; no ; Off ;
Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables.
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter Resource Utilization by Entity ;
-+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
-+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 1058 (1) ; 215 ; 512 ; 2 ; 3 ; 0 ; 843 (1) ; 0 (0) ; 215 (0) ; 214 (0) ; 76 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 100 (94) ; 72 ; 512 ; 2 ; 0 ; 0 ; 28 (22) ; 0 (0) ; 72 (72) ; 11 (11) ; 5 (5) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
-; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
-; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
-; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
-; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 761 (146) ; 67 ; 0 ; 0 ; 0 ; 0 ; 694 (110) ; 0 (0) ; 67 (36) ; 171 (0) ; 70 (39) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 550 (228) ; 0 ; 0 ; 0 ; 0 ; 0 ; 550 (228) ; 0 (0) ; 0 (0) ; 141 (43) ; 31 (31) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
-; |exec_op:add_inst| ; 100 (100) ; 0 ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 0 (0) ; 0 (0) ; 98 (98) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |exec_op:or_inst| ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
-; |exec_op:shift_inst| ; 208 (208) ; 0 ; 0 ; 0 ; 0 ; 0 ; 208 (208) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
-; |extension_gpm:gpmp_inst| ; 65 (65) ; 31 ; 0 ; 0 ; 0 ; 0 ; 34 (34) ; 0 (0) ; 31 (31) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
-; |fetch_stage:fetch_st| ; 33 (24) ; 17 ; 0 ; 0 ; 0 ; 0 ; 16 (13) ; 0 (0) ; 17 (11) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
-; |r_w_ram:instruction_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 163 (48) ; 59 ; 0 ; 0 ; 0 ; 0 ; 104 (44) ; 0 (0) ; 59 (4) ; 32 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st ; ;
-; |extension_uart:uart| ; 106 (12) ; 49 ; 0 ; 0 ; 0 ; 0 ; 57 (2) ; 0 (0) ; 49 (10) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
-; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
-; |r_w_ram:data_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
-+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter Resource Utilization by Entity ;
++----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
+; |core_top ; 1646 (0) ; 520 ; 66560 ; 18 ; 32 ; 0 ; 1126 (0) ; 26 (0) ; 494 (0) ; 184 (0) ; 179 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 212 (150) ; 106 ; 1024 ; 2 ; 0 ; 0 ; 106 (44) ; 0 (0) ; 106 (106) ; 11 (11) ; 3 (3) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 62 (62) ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (62) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 1024 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
+; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
+; |altsyncram:ram_rtl_2| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2 ; ;
+; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 512 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated ; ;
+; |execute_stage:exec_st| ; 836 (137) ; 71 ; 0 ; 0 ; 0 ; 0 ; 765 (98) ; 1 (1) ; 70 (38) ; 108 (0) ; 68 (38) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 637 (324) ; 0 ; 0 ; 0 ; 0 ; 0 ; 637 (324) ; 0 (0) ; 0 (0) ; 78 (44) ; 30 (27) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |exec_op:add_inst| ; 67 (67) ; 0 ; 0 ; 0 ; 0 ; 0 ; 67 (67) ; 0 (0) ; 0 (0) ; 34 (34) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
+; |exec_op:shift_inst| ; 246 (246) ; 0 ; 0 ; 0 ; 0 ; 0 ; 246 (246) ; 0 (0) ; 0 (0) ; 0 (0) ; 3 (3) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
+; |extension_gpm:gpmp_inst| ; 62 (62) ; 32 ; 0 ; 0 ; 0 ; 0 ; 30 (30) ; 0 (0) ; 32 (32) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
+; |fetch_stage:fetch_st| ; 44 (23) ; 29 ; 0 ; 0 ; 0 ; 0 ; 15 (12) ; 0 (0) ; 29 (11) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
+; |rom:instruction_ram| ; 21 (21) ; 18 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 18 (18) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|rom:instruction_ram ; ;
+; |writeback_stage:writeback_st| ; 554 (141) ; 314 ; 65536 ; 16 ; 0 ; 0 ; 240 (77) ; 25 (0) ; 289 (64) ; 65 (0) ; 108 (106) ; |core_top|writeback_stage:writeback_st ; ;
+; |extension_7seg:sseg| ; 47 (47) ; 47 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 17 (17) ; 30 (30) ; 0 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st|extension_7seg:sseg ; ;
+; |extension_uart:uart| ; 366 (144) ; 203 ; 0 ; 0 ; 0 ; 0 ; 163 (38) ; 8 (0) ; 195 (106) ; 65 (0) ; 1 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
+; |rs232_rx:rs232_rx_inst| ; 158 (158) ; 73 ; 0 ; 0 ; 0 ; 0 ; 85 (85) ; 8 (8) ; 65 (65) ; 48 (48) ; 1 (1) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst ; ;
+; |rs232_tx:rs232_tx_inst| ; 64 (64) ; 24 ; 0 ; 0 ; 0 ; 0 ; 40 (40) ; 0 (0) ; 24 (24) ; 17 (17) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
+; |r_w_ram:data_ram| ; 0 (0) ; 0 ; 65536 ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 65536 ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0 ; ;
+; |altsyncram_grk1:auto_generated| ; 0 (0) ; 0 ; 65536 ; 16 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated ; ;
++----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+-------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
-+----------------------------------------------------------------------------------+
-; Delay Chain Summary ;
-+---------+----------+---------------+---------------+-----------------------+-----+
-; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
-+---------+----------+---------------+---------------+-----------------------+-----+
-; bus_tx ; Output ; -- ; -- ; -- ; -- ;
-; sys_clk ; Input ; OFF ; OFF ; -- ; -- ;
-; sys_res ; Input ; OFF ; ON ; -- ; -- ;
-+---------+----------+---------------+---------------+-----------------------+-----+
-
-
-+---------------------------------------------------------------------------------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+---------------------------------------------------------------------------------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------------------------------------------------------------------------------+-------------------+---------+
-; sys_clk ; ; ;
-; sys_res ; ; ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[4] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[6] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[29] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[31] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[30] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[29] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[28] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[27] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[26] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[24] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[18] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[15] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[14] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[12] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[9] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[3] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[2] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg2 ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.wr_en ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.dmem_en ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.alu_jump ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.address[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0 ; 1 ; ON ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[0] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[5] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.daddr[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg1 ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[9] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[8] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[17] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[15] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[16] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[14] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[13] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[11] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[12] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[10] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr_nxt[6]~3 ; 1 ; ON ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[13] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[1] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
-; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[5] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[8] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[9] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.res_addr[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[10] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[11] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[0] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[12] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[1] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[13] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[14] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[15] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[16] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[5] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[17] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[6] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[18] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[7] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[19] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[8] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[20] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[9] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[21] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.prog_cnt[10] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[22] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[23] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[24] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[25] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[26] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[27] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[28] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[29] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
-+---------------------------------------------------------------------------------------------+-------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
-+--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; LC_X39_Y14_N6 ; 57 ; Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X38_Y18_N6 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X36_Y12_N2 ; 30 ; Clock enable ; no ; -- ; -- ;
-; execute_stage:exec_st|reg.result[1]~9 ; LC_X32_Y12_N1 ; 12 ; Sync. load ; no ; -- ; -- ;
-; sys_clk ; PIN_152 ; 217 ; Clock ; yes ; Global Clock ; GCLK7 ;
-; sys_res ; PIN_42 ; 205 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK3 ;
-; writeback_stage:writeback_st|Mux9~0 ; LC_X37_Y15_N8 ; 7 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X32_Y9_N2 ; 5 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X31_Y8_N3 ; 35 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; LC_X36_Y15_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|reg_we~0 ; LC_X35_Y14_N9 ; 8 ; Write enable ; no ; -- ; -- ;
-+--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
++-----------------------------------------------------------------------------------+
+; Delay Chain Summary ;
++----------+----------+---------------+---------------+-----------------------+-----+
+; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ;
++----------+----------+---------------+---------------+-----------------------+-----+
+; bus_tx ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg0[0] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg1[0] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg2[0] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[6] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[5] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[4] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[3] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[2] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[1] ; Output ; -- ; -- ; -- ; -- ;
+; sseg3[0] ; Output ; -- ; -- ; -- ; -- ;
+; sys_clk ; Input ; OFF ; OFF ; -- ; -- ;
+; sys_res ; Input ; OFF ; ON ; -- ; -- ;
+; bus_rx ; Input ; ON ; ON ; -- ; -- ;
++----------+----------+---------------+---------------+-----------------------+-----+
+
+
++---------------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------------------------------------------------------------------------------------+-------------------+---------+
+; sys_clk ; ; ;
+; sys_res ; ; ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[17] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[18] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[19] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[20] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[28] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[29] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[30] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.sel ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.byte_en[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.dmem_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.condition[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.alu_jump ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
+; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~1 ; 1 ; ON ;
+; - decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[2] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.wr_en ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg2 ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[8] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[8] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[9] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[10] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[10] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[12] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[13] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[13] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[15] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg1 ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[17] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[16] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[29] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[30] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[21] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[31] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[31] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[0] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr_nxt[0]~1 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|tx_rdy_int ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.POST_STOP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6]~0 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.IDLE ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5]~2 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7]~4 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4]~6 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2]~8 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1]~10 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3]~12 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[0]~14 ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|bus_rx_int ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[5] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[19] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[18] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[13] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[16] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[8] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[17] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[20] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[5] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[29] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[28] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[21] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[23] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[27] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[25] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[24] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[7] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[4] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[9] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.data[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[10] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.wr_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; 1 ; ON ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
+; bus_rx ; ; ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|sync[1] ; 1 ; ON ;
++---------------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+; decode_stage:decode_st|decoder:decoder_inst|instr_s~10 ; LC_X36_Y12_N6 ; 10 ; Sync. load ; no ; -- ; -- ;
+; decode_stage:decode_st|rtw_rec_nxt.immediate[16]~28 ; LC_X36_Y12_N1 ; 9 ; Sync. clear ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X25_Y16_N7 ; 2 ; Clock enable ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X32_Y18_N0 ; 30 ; Clock enable ; no ; -- ; -- ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; LC_X21_Y16_N1 ; 31 ; Sync. clear ; no ; -- ; -- ;
+; sys_clk ; PIN_152 ; 538 ; Clock ; yes ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 504 ; Async. clear, Async. load, Clock enable ; yes ; Global Clock ; GCLK3 ;
+; writeback_stage:writeback_st|dmem_we~0 ; LC_X22_Y14_N4 ; 16 ; Write enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6]~0 ; LC_X21_Y11_N3 ; 28 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|baud_cnt[4]~33 ; LC_X22_Y18_N2 ; 16 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data ; LC_X22_Y18_N9 ; 9 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[7]~0 ; LC_X22_Y18_N9 ; 9 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; LC_X21_Y19_N3 ; 51 ; Sync. load ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X29_Y8_N2 ; 6 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0]~0 ; LC_X35_Y13_N0 ; 31 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15]~0 ; LC_X30_Y13_N6 ; 32 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0]~1 ; LC_X35_Y13_N9 ; 32 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|reg_we~11 ; LC_X29_Y17_N6 ; 7 ; Write enable ; no ; -- ; -- ;
++----------------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+------------------------------------------------------------------------+
+---------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+---------+----------+---------+----------------------+------------------+
-; sys_clk ; PIN_152 ; 217 ; Global Clock ; GCLK7 ;
-; sys_res ; PIN_42 ; 205 ; Global Clock ; GCLK3 ;
+; sys_clk ; PIN_152 ; 538 ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 504 ; Global Clock ; GCLK3 ;
+---------+----------+---------+----------------------+------------------+
-+---------------------------------------------------------------------------------------------+
-; Non-Global High Fan-Out Signals ;
-+-----------------------------------------------------------------------------------+---------+
-; Name ; Fan-Out ;
-+-----------------------------------------------------------------------------------+---------+
-; execute_stage:exec_st|alu:alu_inst|Selector76~0 ; 114 ;
-; execute_stage:exec_st|right_operand[0]~10 ; 90 ;
-; execute_stage:exec_st|right_operand[1]~6 ; 77 ;
-; execute_stage:exec_st|right_operand[2]~4 ; 64 ;
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 57 ;
-; execute_stage:exec_st|alu:alu_inst|Selector48~0 ; 55 ;
-; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 49 ;
-; execute_stage:exec_st|right_operand[3]~8 ; 48 ;
-; decode_stage:decode_st|dec_op_inst.op_detail[2] ; 41 ;
-; execute_stage:exec_st|left_operand[19]~1 ; 41 ;
-; execute_stage:exec_st|right_operand[30]~2 ; 39 ;
-; execute_stage:exec_st|right_operand[30]~1 ; 39 ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; 37 ;
-; writeback_stage:writeback_st|wb_reg.dmem_en ; 35 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 35 ;
-; writeback_stage:writeback_st|wb_reg.dmem_write_en ; 34 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|Equal0~10 ; 34 ;
-; execute_stage:exec_st|alu:alu_inst|calc~0 ; 32 ;
-; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
-; execute_stage:exec_st|reg.result[7]~12 ; 30 ;
-; execute_stage:exec_st|alu:alu_inst|pwr_en ; 30 ;
-; execute_stage:exec_st|alu:alu_inst|pinc~0 ; 29 ;
-; writeback_stage:writeback_st|jump ; 25 ;
-; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 25 ;
-; execute_stage:exec_st|reg.result[7]~13 ; 24 ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; 24 ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; 23 ;
-; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 20 ;
-; decode_stage:decode_st|decoder:decoder_inst|instr_s~5 ; 15 ;
-; execute_stage:exec_st|reg.result[1]~9 ; 12 ;
-; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 12 ;
-; decode_stage:decode_st|rtw_rec.imm_set ; 12 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 12 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 10 ;
-; execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|tmp_sb~0 ; 9 ;
-; execute_stage:exec_st|alu:alu_inst|Selector76~1 ; 9 ;
-; execute_stage:exec_st|left_operand[30]~46 ; 9 ;
-; execute_stage:exec_st|left_operand[29]~44 ; 9 ;
-; execute_stage:exec_st|left_operand[28]~42 ; 9 ;
-; execute_stage:exec_st|alu:alu_inst|Selector107~0 ; 9 ;
-; execute_stage:exec_st|reg.res_addr[2] ; 9 ;
-; execute_stage:exec_st|reg.result[4]~21 ; 8 ;
-; execute_stage:exec_st|reg.result[25]~14 ; 8 ;
-; execute_stage:exec_st|left_operand[27]~40 ; 8 ;
-; execute_stage:exec_st|left_operand[26]~38 ; 8 ;
-; execute_stage:exec_st|alu:alu_inst|Selector97~0 ; 8 ;
-; execute_stage:exec_st|left_operand[12]~34 ; 8 ;
-; execute_stage:exec_st|left_operand[11]~32 ; 8 ;
-; execute_stage:exec_st|alu:alu_inst|Selector98~0 ; 8 ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; 8 ;
-+-----------------------------------------------------------------------------------+---------+
-
-
-+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Fitter RAM Summary ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
-; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y15 ;
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y14 ;
-+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
++---------------------------------------------------------------------------------------------------+
+; Non-Global High Fan-Out Signals ;
++-----------------------------------------------------------------------------------------+---------+
+; Name ; Fan-Out ;
++-----------------------------------------------------------------------------------------+---------+
+; execute_stage:exec_st|right_operand[0]~19 ; 104 ;
+; execute_stage:exec_st|right_operand[1]~15 ; 98 ;
+; writeback_stage:writeback_st|wb_reg.dmem_en ; 91 ;
+; execute_stage:exec_st|alu:alu_inst|Selector98~0 ; 89 ;
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 78 ;
+; execute_stage:exec_st|right_operand[2]~13 ; 63 ;
+; execute_stage:exec_st|alu:alu_inst|Selector63~0 ; 60 ;
+; execute_stage:exec_st|left_operand[19]~3 ; 59 ;
+; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 53 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; 51 ;
+; writeback_stage:writeback_st|regfile_val[24]~50 ; 48 ;
+; execute_stage:exec_st|right_operand[3]~17 ; 48 ;
+; execute_stage:exec_st|right_operand[5]~3 ; 48 ;
+; execute_stage:exec_st|right_operand[5]~2 ; 48 ;
+; writeback_stage:writeback_st|wb_reg.address[3] ; 45 ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[23] ; 41 ;
+; decode_stage:decode_st|dec_op_inst.op_detail[1] ; 41 ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; 35 ;
+; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 34 ;
+; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ; 33 ;
+; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ; 33 ;
+; writeback_stage:writeback_st|data_addr[12]~10 ; 32 ;
+; writeback_stage:writeback_st|data_addr[11]~9 ; 32 ;
+; writeback_stage:writeback_st|data_addr[10]~8 ; 32 ;
+; writeback_stage:writeback_st|data_addr[9]~7 ; 32 ;
+; writeback_stage:writeback_st|data_addr[8]~6 ; 32 ;
+; writeback_stage:writeback_st|data_addr[7]~5 ; 32 ;
+; writeback_stage:writeback_st|data_addr[6]~4 ; 32 ;
+; writeback_stage:writeback_st|data_addr[5]~3 ; 32 ;
+; writeback_stage:writeback_st|data_addr[4]~2 ; 32 ;
+; writeback_stage:writeback_st|data_addr[3]~1 ; 32 ;
+; writeback_stage:writeback_st|data_addr[2]~0 ; 32 ;
+; execute_stage:exec_st|alu:alu_inst|calc~1 ; 32 ;
+; execute_stage:exec_st|alu:alu_inst|Selector16~2 ; 32 ;
+; execute_stage:exec_st|alu:alu_inst|Selector16~1 ; 32 ;
+; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
+; writeback_stage:writeback_st|extension_uart:uart|w2_uart_config[15]~0 ; 32 ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0]~1 ; 32 ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[22] ; 31 ;
+; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0]~0 ; 31 ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; 30 ;
+; execute_stage:exec_st|alu:alu_inst|pinc~0 ; 29 ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[27] ; 28 ;
+; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6]~0 ; 28 ;
+; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 27 ;
+; writeback_stage:writeback_st|extension_uart:uart|gread~0 ; 27 ;
+; writeback_stage:writeback_st|regfile_val[24]~51 ; 24 ;
+; decode_stage:decode_st|decoder:decoder_inst|instr_spl.bp~0 ; 23 ;
+; decode_stage:decode_st|dec_op_inst.displacement[31] ; 23 ;
+; fetch_stage:fetch_st|rom:instruction_ram|data_out[26] ; 23 ;
++-----------------------------------------------------------------------------------------+---------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Fitter RAM Summary ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 16 ; 32 ; 16 ; 32 ; 512 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y17 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 16 ; 32 ; 16 ; 32 ; 512 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y18 ;
+; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_0|altsyncram_grk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 2048 ; 32 ; 2048 ; 32 ; yes ; no ; yes ; no ; 65536 ; 2048 ; 32 ; 2048 ; 32 ; 65536 ; 16 ; db/dt.ram0_r_w_ram_1e9198d1.hdl.mif ; M4K_X19_Y19, M4K_X33_Y13, M4K_X33_Y14, M4K_X33_Y16, M4K_X19_Y13, M4K_X19_Y16, M4K_X19_Y18, M4K_X19_Y11, M4K_X19_Y15, M4K_X19_Y14, M4K_X19_Y10, M4K_X33_Y11, M4K_X33_Y12, M4K_X33_Y15, M4K_X19_Y17, M4K_X19_Y12 ;
++--------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+-------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
-+-----------------------------------------------------+
-; Interconnect Usage Summary ;
-+----------------------------+------------------------+
-; Interconnect Resource Type ; Usage ;
-+----------------------------+------------------------+
-; C4s ; 1,302 / 30,600 ( 4 % ) ;
-; Direct links ; 132 / 43,552 ( < 1 % ) ;
-; Global clocks ; 2 / 8 ( 25 % ) ;
-; LAB clocks ; 29 / 312 ( 9 % ) ;
-; LUT chains ; 139 / 10,854 ( 1 % ) ;
-; Local interconnects ; 1,864 / 43,552 ( 4 % ) ;
-; M4K buffers ; 64 / 1,872 ( 3 % ) ;
-; R4s ; 1,504 / 28,560 ( 5 % ) ;
-+----------------------------+------------------------+
++------------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+-------------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+-------------------------+
+; C4s ; 3,149 / 30,600 ( 10 % ) ;
+; Direct links ; 169 / 43,552 ( < 1 % ) ;
+; Global clocks ; 2 / 8 ( 25 % ) ;
+; LAB clocks ; 64 / 312 ( 21 % ) ;
+; LUT chains ; 152 / 10,854 ( 1 % ) ;
+; Local interconnects ; 3,313 / 43,552 ( 8 % ) ;
+; M4K buffers ; 96 / 1,872 ( 5 % ) ;
+; R4s ; 3,533 / 28,560 ( 12 % ) ;
++----------------------------+-------------------------+
+----------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-------------------------------+
-; Number of Logic Elements (Average = 9.53) ; Number of LABs (Total = 111) ;
+; Number of Logic Elements (Average = 9.46) ; Number of LABs (Total = 174) ;
+--------------------------------------------+-------------------------------+
-; 1 ; 3 ;
-; 2 ; 2 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
+; 1 ; 4 ;
+; 2 ; 0 ;
+; 3 ; 2 ;
+; 4 ; 2 ;
+; 5 ; 1 ;
; 6 ; 0 ;
-; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 4 ;
-; 10 ; 100 ;
+; 7 ; 2 ;
+; 8 ; 7 ;
+; 9 ; 7 ;
+; 10 ; 149 ;
+--------------------------------------------+-------------------------------+
+--------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-------------------------------+
-; LAB-wide Signals (Average = 1.49) ; Number of LABs (Total = 111) ;
+; LAB-wide Signals (Average = 1.83) ; Number of LABs (Total = 174) ;
+------------------------------------+-------------------------------+
-; 1 Async. clear ; 70 ;
-; 1 Async. load ; 2 ;
-; 1 Clock ; 72 ;
-; 1 Clock enable ; 14 ;
-; 1 Sync. clear ; 2 ;
+; 1 Async. clear ; 126 ;
+; 1 Async. load ; 1 ;
+; 1 Clock ; 130 ;
+; 1 Clock enable ; 39 ;
+; 1 Sync. clear ; 4 ;
; 1 Sync. load ; 5 ;
+; 2 Clock enables ; 14 ;
+------------------------------------+-------------------------------+
+------------------------------------------------------------------------------+
; LAB Signals Sourced ;
+----------------------------------------------+-------------------------------+
-; Number of Signals Sourced (Average = 10.26) ; Number of LABs (Total = 111) ;
+; Number of Signals Sourced (Average = 10.30) ; Number of LABs (Total = 174) ;
+----------------------------------------------+-------------------------------+
; 0 ; 0 ;
-; 1 ; 3 ;
-; 2 ; 2 ;
-; 3 ; 0 ;
-; 4 ; 0 ;
-; 5 ; 0 ;
+; 1 ; 4 ;
+; 2 ; 0 ;
+; 3 ; 2 ;
+; 4 ; 2 ;
+; 5 ; 1 ;
; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 5 ;
-; 10 ; 60 ;
-; 11 ; 19 ;
-; 12 ; 13 ;
-; 13 ; 4 ;
+; 7 ; 2 ;
+; 8 ; 5 ;
+; 9 ; 7 ;
+; 10 ; 87 ;
+; 11 ; 30 ;
+; 12 ; 16 ;
+; 13 ; 6 ;
; 14 ; 5 ;
+; 15 ; 3 ;
+; 16 ; 1 ;
+; 17 ; 3 ;
+----------------------------------------------+-------------------------------+
+---------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-------------------------------+
-; Number of Signals Sourced Out (Average = 6.93) ; Number of LABs (Total = 111) ;
+; Number of Signals Sourced Out (Average = 7.25) ; Number of LABs (Total = 174) ;
+-------------------------------------------------+-------------------------------+
; 0 ; 0 ;
; 1 ; 4 ;
-; 2 ; 2 ;
-; 3 ; 8 ;
-; 4 ; 5 ;
-; 5 ; 11 ;
-; 6 ; 19 ;
-; 7 ; 13 ;
-; 8 ; 15 ;
-; 9 ; 11 ;
-; 10 ; 19 ;
-; 11 ; 2 ;
+; 2 ; 1 ;
+; 3 ; 5 ;
+; 4 ; 9 ;
+; 5 ; 18 ;
+; 6 ; 26 ;
+; 7 ; 33 ;
+; 8 ; 30 ;
+; 9 ; 19 ;
+; 10 ; 21 ;
+; 11 ; 3 ;
; 12 ; 1 ;
; 13 ; 0 ;
; 14 ; 1 ;
+; 15 ; 1 ;
+; 16 ; 2 ;
+-------------------------------------------------+-------------------------------+
+------------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+-------------------------------+
-; Number of Distinct Inputs (Average = 16.28) ; Number of LABs (Total = 111) ;
+; Number of Distinct Inputs (Average = 16.75) ; Number of LABs (Total = 174) ;
+----------------------------------------------+-------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
+; 3 ; 3 ;
+; 4 ; 1 ;
; 5 ; 2 ;
; 6 ; 2 ;
-; 7 ; 0 ;
-; 8 ; 0 ;
-; 9 ; 2 ;
-; 10 ; 4 ;
-; 11 ; 8 ;
-; 12 ; 10 ;
+; 7 ; 6 ;
+; 8 ; 2 ;
+; 9 ; 6 ;
+; 10 ; 6 ;
+; 11 ; 6 ;
+; 12 ; 4 ;
; 13 ; 4 ;
-; 14 ; 4 ;
-; 15 ; 6 ;
+; 14 ; 13 ;
+; 15 ; 10 ;
; 16 ; 5 ;
; 17 ; 4 ;
-; 18 ; 10 ;
-; 19 ; 5 ;
-; 20 ; 19 ;
-; 21 ; 13 ;
-; 22 ; 11 ;
+; 18 ; 9 ;
+; 19 ; 12 ;
+; 20 ; 16 ;
+; 21 ; 35 ;
+; 22 ; 28 ;
+----------------------------------------------+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 12:26:52 2010
+ Info: Processing started: Sun Dec 19 20:36:27 2010
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dt -c dt
Info: Selected device EP1C12Q240C8 for design "dt"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Fitter converted 2 user pins into dedicated programming pins
Info: Pin ~nCSO~ is reserved at location 24
Info: Pin ~ASDO~ is reserved at location 37
+Critical Warning: No exact pin location assignment(s) for 29 pins of 32 total pins
+ Info: Pin sseg0[6] not assigned to an exact location on the device
+ Info: Pin sseg0[5] not assigned to an exact location on the device
+ Info: Pin sseg0[4] not assigned to an exact location on the device
+ Info: Pin sseg0[3] not assigned to an exact location on the device
+ Info: Pin sseg0[2] not assigned to an exact location on the device
+ Info: Pin sseg0[1] not assigned to an exact location on the device
+ Info: Pin sseg0[0] not assigned to an exact location on the device
+ Info: Pin sseg1[6] not assigned to an exact location on the device
+ Info: Pin sseg1[5] not assigned to an exact location on the device
+ Info: Pin sseg1[4] not assigned to an exact location on the device
+ Info: Pin sseg1[3] not assigned to an exact location on the device
+ Info: Pin sseg1[2] not assigned to an exact location on the device
+ Info: Pin sseg1[1] not assigned to an exact location on the device
+ Info: Pin sseg1[0] not assigned to an exact location on the device
+ Info: Pin sseg2[6] not assigned to an exact location on the device
+ Info: Pin sseg2[5] not assigned to an exact location on the device
+ Info: Pin sseg2[4] not assigned to an exact location on the device
+ Info: Pin sseg2[3] not assigned to an exact location on the device
+ Info: Pin sseg2[2] not assigned to an exact location on the device
+ Info: Pin sseg2[1] not assigned to an exact location on the device
+ Info: Pin sseg2[0] not assigned to an exact location on the device
+ Info: Pin sseg3[6] not assigned to an exact location on the device
+ Info: Pin sseg3[5] not assigned to an exact location on the device
+ Info: Pin sseg3[4] not assigned to an exact location on the device
+ Info: Pin sseg3[3] not assigned to an exact location on the device
+ Info: Pin sseg3[2] not assigned to an exact location on the device
+ Info: Pin sseg3[1] not assigned to an exact location on the device
+ Info: Pin sseg3[0] not assigned to an exact location on the device
+ Info: Pin bus_rx not assigned to an exact location on the device
Info: Timing-driven compilation is using the Classic Timing Analyzer
Warning: Classic Timing Analyzer will not be available in a future release of the Quartus II software. Use the TimeQuest Timing Analyzer to run timing analysis on your design. Convert all the project settings and the timing constraints to TimeQuest Timing Analyzer equivalents.
Info: Timing requirements not specified -- quality metrics such as performance and power consumption may be sacrificed to reduce compilation time.
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "sys_clk" to use Global clock in PIN 152
Info: Automatically promoted some destinations of signal "sys_res" to use Global clock
- Info: Destination "execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0" may be non-global or may not use global clock
- Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[6]~3" may be non-global or may not use global clock
+ Info: Destination "execute_stage:exec_st|alu:alu_inst|\calc:cond_met~1" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|new_rx_data" may be non-global or may not use global clock
+ Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[0]~1" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6]~0" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5]~2" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7]~4" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4]~6" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2]~8" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[1]~10" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3]~12" may be non-global or may not use global clock
+ Info: Limited to 10 non-global destinations
Info: Pin "sys_res" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Extra Info: Moving registers into I/O cells, LUTs, and RAM blocks to improve timing and density
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
+Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement
+ Info: Number of I/O pins in group: 29 (unused VREF, 3.3V VCCIO, 1 input, 28 output, 0 bidirectional)
+ Info: I/O standards used: 3.3-V LVCMOS.
+Info: I/O bank details before I/O pin placement
+ Info: Statistics of I/O banks
+ Info: I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 3 total pin(s) used -- 41 pins available
+ Info: I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available
+ Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used -- 43 pins available
+ Info: I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 42 pins available
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Fitter preparation operations ending: elapsed time is 00:00:02
Info: Fitter placement preparation operations beginning
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
-Info: Estimated most critical path is memory to register delay of 21.050 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y15; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg2'
- Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y15; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a6'
- Info: 3: + IC(1.222 ns) + CELL(0.442 ns) = 5.981 ns; Loc. = LAB_X38_Y16; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[6]~17'
- Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 6.634 ns; Loc. = LAB_X38_Y16; Fanout = 4; COMB Node = 'execute_stage:exec_st|left_operand[6]~18'
- Info: 5: + IC(0.117 ns) + CELL(0.590 ns) = 7.341 ns; Loc. = LAB_X38_Y16; Fanout = 9; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector101~0'
- Info: 6: + IC(1.338 ns) + CELL(0.575 ns) = 9.254 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~37COUT1_200'
- Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 9.334 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~27COUT1_202'
- Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 9.414 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~17COUT1_204'
- Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 9.494 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~32COUT1_206'
- Info: 10: + IC(0.000 ns) + CELL(0.258 ns) = 9.752 ns; Loc. = LAB_X30_Y16; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~52'
- Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 9.888 ns; Loc. = LAB_X30_Y16; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~87'
- Info: 12: + IC(0.000 ns) + CELL(0.136 ns) = 10.024 ns; Loc. = LAB_X30_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~117'
- Info: 13: + IC(0.000 ns) + CELL(0.679 ns) = 10.703 ns; Loc. = LAB_X30_Y15; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~120'
- Info: 14: + IC(0.771 ns) + CELL(0.432 ns) = 11.906 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[21]~122COUT1_219'
- Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 11.986 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[22]~127COUT1_221'
- Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 12.066 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[23]~132COUT1_223'
- Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 12.146 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[24]~137COUT1_225'
- Info: 18: + IC(0.000 ns) + CELL(0.258 ns) = 12.404 ns; Loc. = LAB_X31_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[25]~142'
- Info: 19: + IC(0.000 ns) + CELL(0.679 ns) = 13.083 ns; Loc. = LAB_X31_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[28]~65'
- Info: 20: + IC(1.640 ns) + CELL(0.114 ns) = 14.837 ns; Loc. = LAB_X36_Y12; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~0'
- Info: 21: + IC(1.086 ns) + CELL(0.292 ns) = 16.215 ns; Loc. = LAB_X36_Y16; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~1'
- Info: 22: + IC(0.752 ns) + CELL(0.590 ns) = 17.557 ns; Loc. = LAB_X36_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~3'
- Info: 23: + IC(0.539 ns) + CELL(0.114 ns) = 18.210 ns; Loc. = LAB_X36_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
- Info: 24: + IC(0.063 ns) + CELL(0.590 ns) = 18.863 ns; Loc. = LAB_X36_Y15; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
- Info: 25: + IC(0.211 ns) + CELL(0.442 ns) = 19.516 ns; Loc. = LAB_X36_Y15; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
- Info: 26: + IC(0.667 ns) + CELL(0.867 ns) = 21.050 ns; Loc. = LAB_X37_Y15; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]'
- Info: Total cell delay = 12.581 ns ( 59.77 % )
- Info: Total interconnect delay = 8.469 ns ( 40.23 % )
+Info: Estimated most critical path is register to register delay of 23.818 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X35_Y17; Fanout = 2; REG Node = 'writeback_stage:writeback_st|wb_reg.address[16]'
+ Info: 2: + IC(0.860 ns) + CELL(0.114 ns) = 0.974 ns; Loc. = LAB_X36_Y17; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~3'
+ Info: 3: + IC(1.490 ns) + CELL(0.114 ns) = 2.578 ns; Loc. = LAB_X29_Y17; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
+ Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 3.231 ns; Loc. = LAB_X29_Y17; Fanout = 4; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
+ Info: 5: + IC(0.211 ns) + CELL(0.442 ns) = 3.884 ns; Loc. = LAB_X29_Y17; Fanout = 27; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|gread~0'
+ Info: 6: + IC(1.564 ns) + CELL(0.590 ns) = 6.038 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~96'
+ Info: 7: + IC(1.633 ns) + CELL(0.114 ns) = 7.785 ns; Loc. = LAB_X22_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~97'
+ Info: 8: + IC(1.653 ns) + CELL(0.114 ns) = 9.552 ns; Loc. = LAB_X27_Y12; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~98'
+ Info: 9: + IC(0.361 ns) + CELL(0.292 ns) = 10.205 ns; Loc. = LAB_X27_Y12; Fanout = 6; COMB Node = 'writeback_stage:writeback_st|regfile_val[17]~99'
+ Info: 10: + IC(1.177 ns) + CELL(0.114 ns) = 11.496 ns; Loc. = LAB_X29_Y12; Fanout = 1; COMB Node = 'execute_stage:exec_st|right_operand[17]~64'
+ Info: 11: + IC(0.361 ns) + CELL(0.292 ns) = 12.149 ns; Loc. = LAB_X29_Y12; Fanout = 5; COMB Node = 'execute_stage:exec_st|right_operand[17]~65'
+ Info: 12: + IC(1.889 ns) + CELL(0.114 ns) = 14.152 ns; Loc. = LAB_X36_Y11; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~176'
+ Info: 13: + IC(1.431 ns) + CELL(0.575 ns) = 16.158 ns; Loc. = LAB_X31_Y13; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~78COUT1_259'
+ Info: 14: + IC(0.000 ns) + CELL(0.080 ns) = 16.238 ns; Loc. = LAB_X31_Y13; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~73COUT1_261'
+ Info: 15: + IC(0.000 ns) + CELL(0.608 ns) = 16.846 ns; Loc. = LAB_X31_Y13; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add0~66'
+ Info: 16: + IC(1.416 ns) + CELL(0.590 ns) = 18.852 ns; Loc. = LAB_X23_Y12; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector12~2'
+ Info: 17: + IC(0.063 ns) + CELL(0.590 ns) = 19.505 ns; Loc. = LAB_X23_Y12; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector12~5'
+ Info: 18: + IC(0.752 ns) + CELL(0.590 ns) = 20.847 ns; Loc. = LAB_X23_Y11; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Equal0~1'
+ Info: 19: + IC(1.563 ns) + CELL(0.590 ns) = 23.000 ns; Loc. = LAB_X28_Y18; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Equal0~2'
+ Info: 20: + IC(0.211 ns) + CELL(0.607 ns) = 23.818 ns; Loc. = LAB_X28_Y18; Fanout = 1; REG Node = 'execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero'
+ Info: Total cell delay = 7.120 ns ( 29.89 % )
+ Info: Total interconnect delay = 16.698 ns ( 70.11 % )
Info: Fitter routing operations beginning
-Info: Router estimated average interconnect usage is 4% of the available device resources
- Info: Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X32_Y14 to location X42_Y27
-Info: Fitter routing operations ending: elapsed time is 00:00:04
+Info: Router estimated average interconnect usage is 9% of the available device resources
+ Info: Router estimated peak interconnect usage is 35% of the available device resources in the region that extends from location X21_Y14 to location X31_Y27
+Info: Fitter routing operations ending: elapsed time is 00:00:05
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Delay annotation completed successfully
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
-Info: Quartus II Fitter was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 269 megabytes
- Info: Processing ended: Fri Dec 17 12:27:11 2010
- Info: Elapsed time: 00:00:19
- Info: Total CPU time (on all processors): 00:00:19
+Info: Quartus II Fitter was successful. 0 errors, 3 warnings
+ Info: Peak virtual memory: 272 megabytes
+ Info: Processing ended: Sun Dec 19 20:36:45 2010
+ Info: Elapsed time: 00:00:18
+ Info: Total CPU time (on all processors): 00:00:16
projects / calu.git / blobdiff