Fitter report for dt
-Fri Dec 17 10:10:33 2010
+Fri Dec 17 12:27:10 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+-----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------------+
-; Fitter Status ; Successful - Fri Dec 17 10:10:33 2010 ;
+; Fitter Status ; Successful - Fri Dec 17 12:27:10 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
; Device ; EP1C12Q240C8 ;
; Timing Models ; Final ;
-; Total logic elements ; 1,056 / 12,060 ( 9 % ) ;
+; Total logic elements ; 1,058 / 12,060 ( 9 % ) ;
; Total pins ; 3 / 173 ( 2 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
; Type ; Value ;
+---------------------+------------------------+
; Placement (by node) ; ;
-; -- Requested ; 0 / 1125 ( 0.00 % ) ;
-; -- Achieved ; 0 / 1125 ( 0.00 % ) ;
+; -- Requested ; 0 / 1127 ( 0.00 % ) ;
+; -- Achieved ; 0 / 1127 ( 0.00 % ) ;
; ; ;
; Routing (by net) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
-; Top ; 1123 ; 0 ; N/A ; Source File ;
+; Top ; 1125 ; 0 ; N/A ; Source File ;
; hard_block:auto_generated_inst ; 2 ; 0 ; N/A ; Source File ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
+---------------------------------------------+-------------------------------------------------+
; Resource ; Usage ;
+---------------------------------------------+-------------------------------------------------+
-; Total logic elements ; 1,056 / 12,060 ( 9 % ) ;
-; -- Combinational with no register ; 841 ;
+; Total logic elements ; 1,058 / 12,060 ( 9 % ) ;
+; -- Combinational with no register ; 843 ;
; -- Register only ; 0 ;
; -- Combinational with a register ; 215 ;
; ; ;
; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 467 ;
-; -- 3 input functions ; 447 ;
+; -- 4 input functions ; 473 ;
+; -- 3 input functions ; 443 ;
; -- 2 input functions ; 123 ;
; -- 1 input functions ; 18 ;
; -- 0 input functions ; 1 ;
; ; ;
; Logic elements by mode ; ;
-; -- normal mode ; 850 ;
+; -- normal mode ; 852 ;
; -- arithmetic mode ; 206 ;
-; -- qfbk mode ; 77 ;
+; -- qfbk mode ; 76 ;
; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 84 ;
-; -- asynchronous clear/load mode ; 202 ;
+; -- synchronous clear/load mode ; 83 ;
+; -- asynchronous clear/load mode ; 203 ;
; ; ;
; Total registers ; 215 / 12,567 ( 2 % ) ;
-; Total LABs ; 114 / 1,206 ( 9 % ) ;
+; Total LABs ; 111 / 1,206 ( 9 % ) ;
; Logic elements in carry chains ; 214 ;
; User inserted logic elements ; 0 ;
; Virtual pins ; 0 ;
; JTAGs ; 0 / 1 ( 0 % ) ;
; ASMI Blocks ; 0 / 1 ( 0 % ) ;
; CRC blocks ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 5% / 5% / 5% ;
-; Peak interconnect usage (total/H/V) ; 31% / 32% / 30% ;
+; Average interconnect usage (total/H/V) ; 5% / 5% / 4% ;
+; Peak interconnect usage (total/H/V) ; 17% / 19% / 14% ;
; Maximum fan-out node ; sys_clk ;
; Maximum fan-out ; 217 ;
; Highest non-global fan-out signal ; execute_stage:exec_st|alu:alu_inst|Selector76~0 ;
-; Highest non-global fan-out ; 115 ;
-; Total fan-out ; 4170 ;
-; Average fan-out ; 3.92 ;
+; Highest non-global fan-out ; 114 ;
+; Total fan-out ; 4182 ;
+; Average fan-out ; 3.93 ;
+---------------------------------------------+-------------------------------------------------+
+---------------------------------------------+--------------------+--------------------------------+
; Difficulty Clustering Region ; Low ; Low ;
; ; ; ;
-; Total logic elements ; 1056 ; 0 ;
-; -- Combinational with no register ; 841 ; 0 ;
+; Total logic elements ; 1058 ; 0 ;
+; -- Combinational with no register ; 843 ; 0 ;
; -- Register only ; 0 ; 0 ;
; -- Combinational with a register ; 215 ; 0 ;
; ; ; ;
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
-; -- Total Connections ; 4343 ; 0 ;
-; -- Registered Connections ; 813 ; 0 ;
+; -- Total Connections ; 4355 ; 0 ;
+; -- Registered Connections ; 809 ; 0 ;
; ; ; ;
; External Connections ; ; ;
; -- Top ; 0 ; 0 ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 1056 (1) ; 215 ; 512 ; 2 ; 3 ; 0 ; 841 (1) ; 0 (0) ; 215 (0) ; 214 (0) ; 77 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 103 (96) ; 72 ; 512 ; 2 ; 0 ; 0 ; 31 (24) ; 0 (0) ; 72 (72) ; 11 (11) ; 5 (5) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |core_top ; 1058 (1) ; 215 ; 512 ; 2 ; 3 ; 0 ; 843 (1) ; 0 (0) ; 215 (0) ; 214 (0) ; 76 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 100 (94) ; 72 ; 512 ; 2 ; 0 ; 0 ; 28 (22) ; 0 (0) ; 72 (72) ; 11 (11) ; 5 (5) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 6 (6) ; 0 ; 0 ; 0 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 755 (145) ; 67 ; 0 ; 0 ; 0 ; 0 ; 688 (109) ; 0 (0) ; 67 (36) ; 171 (0) ; 71 (40) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 545 (224) ; 0 ; 0 ; 0 ; 0 ; 0 ; 545 (224) ; 0 (0) ; 0 (0) ; 141 (43) ; 31 (31) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |execute_stage:exec_st| ; 761 (146) ; 67 ; 0 ; 0 ; 0 ; 0 ; 694 (110) ; 0 (0) ; 67 (36) ; 171 (0) ; 70 (39) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 550 (228) ; 0 ; 0 ; 0 ; 0 ; 0 ; 550 (228) ; 0 (0) ; 0 (0) ; 141 (43) ; 31 (31) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
; |exec_op:add_inst| ; 100 (100) ; 0 ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 0 (0) ; 0 (0) ; 98 (98) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |exec_op:or_inst| ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
+; |exec_op:or_inst| ; 14 (14) ; 0 ; 0 ; 0 ; 0 ; 0 ; 14 (14) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
; |exec_op:shift_inst| ; 208 (208) ; 0 ; 0 ; 0 ; 0 ; 0 ; 208 (208) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
; |extension_gpm:gpmp_inst| ; 65 (65) ; 31 ; 0 ; 0 ; 0 ; 0 ; 34 (34) ; 0 (0) ; 31 (31) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
; |fetch_stage:fetch_st| ; 33 (24) ; 17 ; 0 ; 0 ; 0 ; 0 ; 16 (13) ; 0 (0) ; 17 (11) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
; |r_w_ram:instruction_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 164 (52) ; 59 ; 0 ; 0 ; 0 ; 0 ; 105 (48) ; 0 (0) ; 59 (4) ; 32 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st ; ;
+; |writeback_stage:writeback_st| ; 163 (48) ; 59 ; 0 ; 0 ; 0 ; 0 ; 104 (44) ; 0 (0) ; 59 (4) ; 32 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st ; ;
; |extension_uart:uart| ; 106 (12) ; 49 ; 0 ; 0 ; 0 ; 0 ; 57 (2) ; 0 (0) ; 49 (10) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
-; |r_w_ram:data_ram| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+; |r_w_ram:data_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0 ; 1 ; ON ;
; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.displacement[3] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
-; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr_nxt[3]~3 ; 1 ; ON ;
+; - fetch_stage:fetch_st|instr_r_addr_nxt[6]~3 ; 1 ; ON ;
; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[13] ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|dec_op_inst.saddr1[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[1] ; 0 ; OFF ;
; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
-; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 1 ; ON ;
+; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
-; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
-; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
-; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
+---------------------------------------------------------------------------------------------+-------------------+---------+
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
-+--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; LC_X27_Y17_N9 ; 58 ; Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X36_Y17_N6 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X29_Y15_N2 ; 30 ; Clock enable ; no ; -- ; -- ;
-; execute_stage:exec_st|reg.result[1]~9 ; LC_X27_Y16_N4 ; 12 ; Sync. load ; no ; -- ; -- ;
-; sys_clk ; PIN_152 ; 217 ; Clock ; yes ; Global Clock ; GCLK7 ;
-; sys_res ; PIN_42 ; 205 ; Async. clear, Async. load, Clock enable ; yes ; Global Clock ; GCLK3 ;
-; writeback_stage:writeback_st|Mux9~0 ; LC_X26_Y19_N7 ; 7 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X40_Y20_N6 ; 5 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X40_Y19_N5 ; 35 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; LC_X27_Y19_N6 ; 8 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|reg_we~0 ; LC_X31_Y18_N0 ; 8 ; Write enable ; no ; -- ; -- ;
-+--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; LC_X39_Y14_N6 ; 57 ; Sync. load ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X38_Y18_N6 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X36_Y12_N2 ; 30 ; Clock enable ; no ; -- ; -- ;
+; execute_stage:exec_st|reg.result[1]~9 ; LC_X32_Y12_N1 ; 12 ; Sync. load ; no ; -- ; -- ;
+; sys_clk ; PIN_152 ; 217 ; Clock ; yes ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 205 ; Async. clear, Async. load ; yes ; Global Clock ; GCLK3 ;
+; writeback_stage:writeback_st|Mux9~0 ; LC_X37_Y15_N8 ; 7 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X32_Y9_N2 ; 5 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X31_Y8_N3 ; 35 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; LC_X36_Y15_N2 ; 8 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|reg_we~0 ; LC_X35_Y14_N9 ; 8 ; Write enable ; no ; -- ; -- ;
++--------------------------------------------------------------------------------------+---------------+---------+---------------------------+--------+----------------------+------------------+
+------------------------------------------------------------------------+
+-----------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+-----------------------------------------------------------------------------------+---------+
-; execute_stage:exec_st|alu:alu_inst|Selector76~0 ; 115 ;
-; execute_stage:exec_st|right_operand[0]~10 ; 89 ;
+; execute_stage:exec_st|alu:alu_inst|Selector76~0 ; 114 ;
+; execute_stage:exec_st|right_operand[0]~10 ; 90 ;
; execute_stage:exec_st|right_operand[1]~6 ; 77 ;
-; execute_stage:exec_st|right_operand[2]~4 ; 63 ;
-; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 58 ;
-; execute_stage:exec_st|alu:alu_inst|Selector53~0 ; 53 ;
+; execute_stage:exec_st|right_operand[2]~4 ; 64 ;
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 57 ;
+; execute_stage:exec_st|alu:alu_inst|Selector48~0 ; 55 ;
; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 49 ;
; execute_stage:exec_st|right_operand[3]~8 ; 48 ;
; decode_stage:decode_st|dec_op_inst.op_detail[2] ; 41 ;
-; execute_stage:exec_st|left_operand[13]~1 ; 40 ;
-; execute_stage:exec_st|right_operand[14]~1 ; 38 ;
+; execute_stage:exec_st|left_operand[19]~1 ; 41 ;
+; execute_stage:exec_st|right_operand[30]~2 ; 39 ;
+; execute_stage:exec_st|right_operand[30]~1 ; 39 ;
; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; 37 ;
-; execute_stage:exec_st|right_operand[14]~2 ; 37 ;
; writeback_stage:writeback_st|wb_reg.dmem_en ; 35 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 35 ;
; writeback_stage:writeback_st|wb_reg.dmem_write_en ; 34 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|Equal0~10 ; 34 ;
; execute_stage:exec_st|alu:alu_inst|calc~0 ; 32 ;
; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
+; execute_stage:exec_st|reg.result[7]~12 ; 30 ;
; execute_stage:exec_st|alu:alu_inst|pwr_en ; 30 ;
-; execute_stage:exec_st|reg.result[11]~12 ; 29 ;
; execute_stage:exec_st|alu:alu_inst|pinc~0 ; 29 ;
; writeback_stage:writeback_st|jump ; 25 ;
; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 25 ;
+; execute_stage:exec_st|reg.result[7]~13 ; 24 ;
; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; 24 ;
-; execute_stage:exec_st|reg.result[11]~13 ; 23 ;
; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; 23 ;
-; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 21 ;
+; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 20 ;
; decode_stage:decode_st|decoder:decoder_inst|instr_s~5 ; 15 ;
-; decode_stage:decode_st|rtw_rec.imm_set ; 15 ;
-; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 13 ;
; execute_stage:exec_st|reg.result[1]~9 ; 12 ;
+; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 12 ;
+; decode_stage:decode_st|rtw_rec.imm_set ; 12 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 12 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 10 ;
; execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|tmp_sb~0 ; 9 ;
-; execute_stage:exec_st|left_operand[30]~56 ; 9 ;
-; execute_stage:exec_st|left_operand[29]~54 ; 9 ;
-; execute_stage:exec_st|left_operand[28]~52 ; 9 ;
+; execute_stage:exec_st|alu:alu_inst|Selector76~1 ; 9 ;
+; execute_stage:exec_st|left_operand[30]~46 ; 9 ;
+; execute_stage:exec_st|left_operand[29]~44 ; 9 ;
+; execute_stage:exec_st|left_operand[28]~42 ; 9 ;
+; execute_stage:exec_st|alu:alu_inst|Selector107~0 ; 9 ;
; execute_stage:exec_st|reg.res_addr[2] ; 9 ;
-; execute_stage:exec_st|reg.result[6]~21 ; 8 ;
+; execute_stage:exec_st|reg.result[4]~21 ; 8 ;
; execute_stage:exec_st|reg.result[25]~14 ; 8 ;
-; execute_stage:exec_st|alu:alu_inst|Selector76~1 ; 8 ;
-; execute_stage:exec_st|left_operand[27]~50 ; 8 ;
-; execute_stage:exec_st|left_operand[26]~48 ; 8 ;
+; execute_stage:exec_st|left_operand[27]~40 ; 8 ;
+; execute_stage:exec_st|left_operand[26]~38 ; 8 ;
; execute_stage:exec_st|alu:alu_inst|Selector97~0 ; 8 ;
; execute_stage:exec_st|left_operand[12]~34 ; 8 ;
; execute_stage:exec_st|left_operand[11]~32 ; 8 ;
; execute_stage:exec_st|alu:alu_inst|Selector98~0 ; 8 ;
-; execute_stage:exec_st|alu:alu_inst|Selector107~0 ; 8 ;
-; execute_stage:exec_st|right_operand[14]~13 ; 8 ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; 8 ;
+-----------------------------------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y18 ;
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y19 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y15 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y14 ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
+----------------------------+------------------------+
; Interconnect Resource Type ; Usage ;
+----------------------------+------------------------+
-; C4s ; 1,397 / 30,600 ( 5 % ) ;
-; Direct links ; 137 / 43,552 ( < 1 % ) ;
+; C4s ; 1,302 / 30,600 ( 4 % ) ;
+; Direct links ; 132 / 43,552 ( < 1 % ) ;
; Global clocks ; 2 / 8 ( 25 % ) ;
-; LAB clocks ; 32 / 312 ( 10 % ) ;
-; LUT chains ; 146 / 10,854 ( 1 % ) ;
-; Local interconnects ; 1,899 / 43,552 ( 4 % ) ;
+; LAB clocks ; 29 / 312 ( 9 % ) ;
+; LUT chains ; 139 / 10,854 ( 1 % ) ;
+; Local interconnects ; 1,864 / 43,552 ( 4 % ) ;
; M4K buffers ; 64 / 1,872 ( 3 % ) ;
-; R4s ; 1,532 / 28,560 ( 5 % ) ;
+; R4s ; 1,504 / 28,560 ( 5 % ) ;
+----------------------------+------------------------+
+----------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+-------------------------------+
-; Number of Logic Elements (Average = 9.26) ; Number of LABs (Total = 114) ;
+; Number of Logic Elements (Average = 9.53) ; Number of LABs (Total = 111) ;
+--------------------------------------------+-------------------------------+
-; 1 ; 6 ;
-; 2 ; 1 ;
-; 3 ; 1 ;
+; 1 ; 3 ;
+; 2 ; 2 ;
+; 3 ; 0 ;
; 4 ; 0 ;
-; 5 ; 2 ;
+; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
-; 8 ; 0 ;
-; 9 ; 2 ;
-; 10 ; 101 ;
+; 8 ; 1 ;
+; 9 ; 4 ;
+; 10 ; 100 ;
+--------------------------------------------+-------------------------------+
+--------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+-------------------------------+
-; LAB-wide Signals (Average = 1.44) ; Number of LABs (Total = 114) ;
+; LAB-wide Signals (Average = 1.49) ; Number of LABs (Total = 111) ;
+------------------------------------+-------------------------------+
-; 1 Async. clear ; 69 ;
+; 1 Async. clear ; 70 ;
; 1 Async. load ; 2 ;
; 1 Clock ; 72 ;
-; 1 Clock enable ; 13 ;
-; 1 Sync. clear ; 3 ;
+; 1 Clock enable ; 14 ;
+; 1 Sync. clear ; 2 ;
; 1 Sync. load ; 5 ;
+------------------------------------+-------------------------------+
-+-----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+-------------------------------+
-; Number of Signals Sourced (Average = 9.97) ; Number of LABs (Total = 114) ;
-+---------------------------------------------+-------------------------------+
-; 0 ; 0 ;
-; 1 ; 6 ;
-; 2 ; 1 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 2 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 1 ;
-; 9 ; 2 ;
-; 10 ; 60 ;
-; 11 ; 21 ;
-; 12 ; 7 ;
-; 13 ; 7 ;
-; 14 ; 6 ;
-+---------------------------------------------+-------------------------------+
++------------------------------------------------------------------------------+
+; LAB Signals Sourced ;
++----------------------------------------------+-------------------------------+
+; Number of Signals Sourced (Average = 10.26) ; Number of LABs (Total = 111) ;
++----------------------------------------------+-------------------------------+
+; 0 ; 0 ;
+; 1 ; 3 ;
+; 2 ; 2 ;
+; 3 ; 0 ;
+; 4 ; 0 ;
+; 5 ; 0 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 0 ;
+; 9 ; 5 ;
+; 10 ; 60 ;
+; 11 ; 19 ;
+; 12 ; 13 ;
+; 13 ; 4 ;
+; 14 ; 5 ;
++----------------------------------------------+-------------------------------+
+---------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+-------------------------------+
-; Number of Signals Sourced Out (Average = 6.84) ; Number of LABs (Total = 114) ;
+; Number of Signals Sourced Out (Average = 6.93) ; Number of LABs (Total = 111) ;
+-------------------------------------------------+-------------------------------+
; 0 ; 0 ;
-; 1 ; 6 ;
-; 2 ; 1 ;
-; 3 ; 7 ;
-; 4 ; 7 ;
-; 5 ; 14 ;
-; 6 ; 15 ;
-; 7 ; 14 ;
-; 8 ; 17 ;
-; 9 ; 10 ;
-; 10 ; 18 ;
+; 1 ; 4 ;
+; 2 ; 2 ;
+; 3 ; 8 ;
+; 4 ; 5 ;
+; 5 ; 11 ;
+; 6 ; 19 ;
+; 7 ; 13 ;
+; 8 ; 15 ;
+; 9 ; 11 ;
+; 10 ; 19 ;
; 11 ; 2 ;
-; 12 ; 2 ;
-; 13 ; 1 ;
+; 12 ; 1 ;
+; 13 ; 0 ;
+; 14 ; 1 ;
+-------------------------------------------------+-------------------------------+
+------------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+----------------------------------------------+-------------------------------+
-; Number of Distinct Inputs (Average = 16.04) ; Number of LABs (Total = 114) ;
+; Number of Distinct Inputs (Average = 16.28) ; Number of LABs (Total = 111) ;
+----------------------------------------------+-------------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
-; 3 ; 3 ;
-; 4 ; 1 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
; 5 ; 2 ;
-; 6 ; 1 ;
+; 6 ; 2 ;
; 7 ; 0 ;
-; 8 ; 2 ;
-; 9 ; 0 ;
-; 10 ; 5 ;
+; 8 ; 0 ;
+; 9 ; 2 ;
+; 10 ; 4 ;
; 11 ; 8 ;
-; 12 ; 7 ;
-; 13 ; 3 ;
-; 14 ; 9 ;
-; 15 ; 5 ;
+; 12 ; 10 ;
+; 13 ; 4 ;
+; 14 ; 4 ;
+; 15 ; 6 ;
; 16 ; 5 ;
-; 17 ; 6 ;
-; 18 ; 7 ;
-; 19 ; 4 ;
-; 20 ; 18 ;
-; 21 ; 16 ;
+; 17 ; 4 ;
+; 18 ; 10 ;
+; 19 ; 5 ;
+; 20 ; 19 ;
+; 21 ; 13 ;
; 22 ; 11 ;
+----------------------------------------------+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Fri Dec 17 10:10:15 2010
+ Info: Processing started: Fri Dec 17 12:26:52 2010
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dt -c dt
Info: Selected device EP1C12Q240C8 for design "dt"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Automatically promoted signal "sys_clk" to use Global clock in PIN 152
Info: Automatically promoted some destinations of signal "sys_res" to use Global clock
Info: Destination "execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0" may be non-global or may not use global clock
- Info: Destination "writeback_stage:writeback_st|extension_uart:uart|new_tx_data" may be non-global or may not use global clock
- Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[3]~3" may be non-global or may not use global clock
+ Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[6]~3" may be non-global or may not use global clock
Info: Pin "sys_res" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Fitter placement operations ending: elapsed time is 00:00:02
-Info: Estimated most critical path is memory to register delay of 20.863 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3~portb_address_reg2'
- Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3'
- Info: 3: + IC(1.586 ns) + CELL(0.442 ns) = 6.345 ns; Loc. = LAB_X28_Y22; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[3]~19'
- Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 6.998 ns; Loc. = LAB_X28_Y22; Fanout = 4; COMB Node = 'execute_stage:exec_st|left_operand[3]~20'
- Info: 5: + IC(0.117 ns) + CELL(0.590 ns) = 7.705 ns; Loc. = LAB_X28_Y22; Fanout = 8; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector104~0'
- Info: 6: + IC(0.995 ns) + CELL(0.575 ns) = 9.275 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~2COUT1_196'
- Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 9.355 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~12COUT1_198'
- Info: 8: + IC(0.000 ns) + CELL(0.258 ns) = 9.613 ns; Loc. = LAB_X31_Y22; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~17'
- Info: 9: + IC(0.000 ns) + CELL(0.679 ns) = 10.292 ns; Loc. = LAB_X31_Y21; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~20'
- Info: 10: + IC(0.771 ns) + CELL(0.432 ns) = 11.495 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[6]~22COUT1_195'
- Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 11.575 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[7]~27COUT1_197'
- Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 11.655 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[8]~32COUT1_199'
- Info: 13: + IC(0.000 ns) + CELL(0.608 ns) = 12.263 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[9]~5'
- Info: 14: + IC(1.264 ns) + CELL(0.114 ns) = 13.641 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector65~0'
- Info: 15: + IC(0.361 ns) + CELL(0.292 ns) = 14.294 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector65~1'
- Info: 16: + IC(0.063 ns) + CELL(0.590 ns) = 14.947 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~0'
- Info: 17: + IC(0.303 ns) + CELL(0.590 ns) = 15.840 ns; Loc. = LAB_X30_Y17; Fanout = 7; COMB Node = 'writeback_stage:writeback_st|Equal0~5'
- Info: 18: + IC(1.093 ns) + CELL(0.590 ns) = 17.523 ns; Loc. = LAB_X27_Y19; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
- Info: 19: + IC(0.063 ns) + CELL(0.590 ns) = 18.176 ns; Loc. = LAB_X27_Y19; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~12'
- Info: 20: + IC(0.211 ns) + CELL(0.442 ns) = 18.829 ns; Loc. = LAB_X27_Y19; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
- Info: 21: + IC(1.167 ns) + CELL(0.867 ns) = 20.863 ns; Loc. = LAB_X28_Y21; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
- Info: Total cell delay = 12.806 ns ( 61.38 % )
- Info: Total interconnect delay = 8.057 ns ( 38.62 % )
+Info: Estimated most critical path is memory to register delay of 21.050 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y15; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a6~portb_address_reg2'
+ Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y15; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a6'
+ Info: 3: + IC(1.222 ns) + CELL(0.442 ns) = 5.981 ns; Loc. = LAB_X38_Y16; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[6]~17'
+ Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 6.634 ns; Loc. = LAB_X38_Y16; Fanout = 4; COMB Node = 'execute_stage:exec_st|left_operand[6]~18'
+ Info: 5: + IC(0.117 ns) + CELL(0.590 ns) = 7.341 ns; Loc. = LAB_X38_Y16; Fanout = 9; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector101~0'
+ Info: 6: + IC(1.338 ns) + CELL(0.575 ns) = 9.254 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~37COUT1_200'
+ Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 9.334 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~27COUT1_202'
+ Info: 8: + IC(0.000 ns) + CELL(0.080 ns) = 9.414 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~17COUT1_204'
+ Info: 9: + IC(0.000 ns) + CELL(0.080 ns) = 9.494 ns; Loc. = LAB_X30_Y16; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~32COUT1_206'
+ Info: 10: + IC(0.000 ns) + CELL(0.258 ns) = 9.752 ns; Loc. = LAB_X30_Y16; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~52'
+ Info: 11: + IC(0.000 ns) + CELL(0.136 ns) = 9.888 ns; Loc. = LAB_X30_Y16; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~87'
+ Info: 12: + IC(0.000 ns) + CELL(0.136 ns) = 10.024 ns; Loc. = LAB_X30_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~117'
+ Info: 13: + IC(0.000 ns) + CELL(0.679 ns) = 10.703 ns; Loc. = LAB_X30_Y15; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~120'
+ Info: 14: + IC(0.771 ns) + CELL(0.432 ns) = 11.906 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[21]~122COUT1_219'
+ Info: 15: + IC(0.000 ns) + CELL(0.080 ns) = 11.986 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[22]~127COUT1_221'
+ Info: 16: + IC(0.000 ns) + CELL(0.080 ns) = 12.066 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[23]~132COUT1_223'
+ Info: 17: + IC(0.000 ns) + CELL(0.080 ns) = 12.146 ns; Loc. = LAB_X31_Y15; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[24]~137COUT1_225'
+ Info: 18: + IC(0.000 ns) + CELL(0.258 ns) = 12.404 ns; Loc. = LAB_X31_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[25]~142'
+ Info: 19: + IC(0.000 ns) + CELL(0.679 ns) = 13.083 ns; Loc. = LAB_X31_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[28]~65'
+ Info: 20: + IC(1.640 ns) + CELL(0.114 ns) = 14.837 ns; Loc. = LAB_X36_Y12; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~0'
+ Info: 21: + IC(1.086 ns) + CELL(0.292 ns) = 16.215 ns; Loc. = LAB_X36_Y16; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector46~1'
+ Info: 22: + IC(0.752 ns) + CELL(0.590 ns) = 17.557 ns; Loc. = LAB_X36_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~3'
+ Info: 23: + IC(0.539 ns) + CELL(0.114 ns) = 18.210 ns; Loc. = LAB_X36_Y15; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
+ Info: 24: + IC(0.063 ns) + CELL(0.590 ns) = 18.863 ns; Loc. = LAB_X36_Y15; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
+ Info: 25: + IC(0.211 ns) + CELL(0.442 ns) = 19.516 ns; Loc. = LAB_X36_Y15; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
+ Info: 26: + IC(0.667 ns) + CELL(0.867 ns) = 21.050 ns; Loc. = LAB_X37_Y15; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2]'
+ Info: Total cell delay = 12.581 ns ( 59.77 % )
+ Info: Total interconnect delay = 8.469 ns ( 40.23 % )
Info: Fitter routing operations beginning
Info: Router estimated average interconnect usage is 4% of the available device resources
- Info: Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X21_Y14 to location X31_Y27
+ Info: Router estimated peak interconnect usage is 14% of the available device resources in the region that extends from location X32_Y14 to location X42_Y27
Info: Fitter routing operations ending: elapsed time is 00:00:04
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 269 megabytes
- Info: Processing ended: Fri Dec 17 10:10:34 2010
+ Info: Processing ended: Fri Dec 17 12:27:11 2010
Info: Elapsed time: 00:00:19
Info: Total CPU time (on all processors): 00:00:19
projects / calu.git / blobdiff