Fitter report for dt
-Thu Dec 16 16:54:58 2010
+Fri Dec 17 10:10:33 2010
Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+-----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+-----------------------------------------------+
-; Fitter Status ; Successful - Thu Dec 16 16:54:57 2010 ;
+; Fitter Status ; Successful - Fri Dec 17 10:10:33 2010 ;
; Quartus II Version ; 10.0 Build 262 08/18/2010 SP 1 SJ Web Edition ;
; Revision Name ; dt ;
; Top-level Entity Name ; core_top ;
; Family ; Cyclone ;
; Device ; EP1C12Q240C8 ;
; Timing Models ; Final ;
-; Total logic elements ; 398 / 12,060 ( 3 % ) ;
-; Total pins ; 2 / 173 ( 1 % ) ;
+; Total logic elements ; 1,056 / 12,060 ( 9 % ) ;
+; Total pins ; 3 / 173 ( 2 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
; Type ; Value ;
+---------------------+------------------------+
; Placement (by node) ; ;
-; -- Requested ; 0 / 466 ( 0.00 % ) ;
-; -- Achieved ; 0 / 466 ( 0.00 % ) ;
+; -- Requested ; 0 / 1125 ( 0.00 % ) ;
+; -- Achieved ; 0 / 1125 ( 0.00 % ) ;
; ; ;
; Routing (by net) ; ;
; -- Requested ; 0 / 0 ( 0.00 % ) ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
-; Top ; 464 ; 0 ; N/A ; Source File ;
+; Top ; 1123 ; 0 ; N/A ; Source File ;
; hard_block:auto_generated_inst ; 2 ; 0 ; N/A ; Source File ;
+--------------------------------+---------+-------------------+-------------------------+-------------------+
+--------------+
; Pin-Out File ;
+--------------+
-The pin-out file can be found in /homes/burban/calu/dt/dt.pin.
-
-
-+-------------------------------------------------------------------------------------------+
-; Fitter Resource Usage Summary ;
-+---------------------------------------------+---------------------------------------------+
-; Resource ; Usage ;
-+---------------------------------------------+---------------------------------------------+
-; Total logic elements ; 398 / 12,060 ( 3 % ) ;
-; -- Combinational with no register ; 257 ;
-; -- Register only ; 12 ;
-; -- Combinational with a register ; 129 ;
-; ; ;
-; Logic element usage by number of LUT inputs ; ;
-; -- 4 input functions ; 105 ;
-; -- 3 input functions ; 195 ;
-; -- 2 input functions ; 80 ;
-; -- 1 input functions ; 4 ;
-; -- 0 input functions ; 2 ;
-; ; ;
-; Logic elements by mode ; ;
-; -- normal mode ; 298 ;
-; -- arithmetic mode ; 100 ;
-; -- qfbk mode ; 35 ;
-; -- register cascade mode ; 0 ;
-; -- synchronous clear/load mode ; 44 ;
-; -- asynchronous clear/load mode ; 0 ;
-; ; ;
-; Total registers ; 141 / 12,567 ( 1 % ) ;
-; Total LABs ; 48 / 1,206 ( 4 % ) ;
-; Logic elements in carry chains ; 104 ;
-; User inserted logic elements ; 0 ;
-; Virtual pins ; 0 ;
-; I/O pins ; 2 / 173 ( 1 % ) ;
-; -- Clock pins ; 1 / 2 ( 50 % ) ;
-; Global signals ; 1 ;
-; M4Ks ; 2 / 52 ( 4 % ) ;
-; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
-; Total RAM block bits ; 9,216 / 239,616 ( 4 % ) ;
-; PLLs ; 0 / 2 ( 0 % ) ;
-; Global clocks ; 1 / 8 ( 13 % ) ;
-; JTAGs ; 0 / 1 ( 0 % ) ;
-; ASMI Blocks ; 0 / 1 ( 0 % ) ;
-; CRC blocks ; 0 / 1 ( 0 % ) ;
-; Average interconnect usage (total/H/V) ; 1% / 1% / 1% ;
-; Peak interconnect usage (total/H/V) ; 4% / 5% / 4% ;
-; Maximum fan-out node ; sys_clk ;
-; Maximum fan-out ; 143 ;
-; Highest non-global fan-out signal ; decode_stage:decode_st|rtw_rec.immediate[3] ;
-; Highest non-global fan-out ; 66 ;
-; Total fan-out ; 1487 ;
-; Average fan-out ; 3.68 ;
-+---------------------------------------------+---------------------------------------------+
+The pin-out file can be found in /homes/c0726283/calu/dt/dt.pin.
+
+
++-----------------------------------------------------------------------------------------------+
+; Fitter Resource Usage Summary ;
++---------------------------------------------+-------------------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+-------------------------------------------------+
+; Total logic elements ; 1,056 / 12,060 ( 9 % ) ;
+; -- Combinational with no register ; 841 ;
+; -- Register only ; 0 ;
+; -- Combinational with a register ; 215 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 467 ;
+; -- 3 input functions ; 447 ;
+; -- 2 input functions ; 123 ;
+; -- 1 input functions ; 18 ;
+; -- 0 input functions ; 1 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 850 ;
+; -- arithmetic mode ; 206 ;
+; -- qfbk mode ; 77 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 84 ;
+; -- asynchronous clear/load mode ; 202 ;
+; ; ;
+; Total registers ; 215 / 12,567 ( 2 % ) ;
+; Total LABs ; 114 / 1,206 ( 9 % ) ;
+; Logic elements in carry chains ; 214 ;
+; User inserted logic elements ; 0 ;
+; Virtual pins ; 0 ;
+; I/O pins ; 3 / 173 ( 2 % ) ;
+; -- Clock pins ; 1 / 2 ( 50 % ) ;
+; Global signals ; 2 ;
+; M4Ks ; 2 / 52 ( 4 % ) ;
+; Total memory bits ; 512 / 239,616 ( < 1 % ) ;
+; Total RAM block bits ; 9,216 / 239,616 ( 4 % ) ;
+; PLLs ; 0 / 2 ( 0 % ) ;
+; Global clocks ; 2 / 8 ( 25 % ) ;
+; JTAGs ; 0 / 1 ( 0 % ) ;
+; ASMI Blocks ; 0 / 1 ( 0 % ) ;
+; CRC blocks ; 0 / 1 ( 0 % ) ;
+; Average interconnect usage (total/H/V) ; 5% / 5% / 5% ;
+; Peak interconnect usage (total/H/V) ; 31% / 32% / 30% ;
+; Maximum fan-out node ; sys_clk ;
+; Maximum fan-out ; 217 ;
+; Highest non-global fan-out signal ; execute_stage:exec_st|alu:alu_inst|Selector76~0 ;
+; Highest non-global fan-out ; 115 ;
+; Total fan-out ; 4170 ;
+; Average fan-out ; 3.92 ;
++---------------------------------------------+-------------------------------------------------+
+---------------------------------------------------------------------------------------------------+
+---------------------------------------------+--------------------+--------------------------------+
; Difficulty Clustering Region ; Low ; Low ;
; ; ; ;
-; Total logic elements ; 398 ; 0 ;
-; -- Combinational with no register ; 257 ; 0 ;
-; -- Register only ; 12 ; 0 ;
-; -- Combinational with a register ; 129 ; 0 ;
+; Total logic elements ; 1056 ; 0 ;
+; -- Combinational with no register ; 841 ; 0 ;
+; -- Register only ; 0 ; 0 ;
+; -- Combinational with a register ; 215 ; 0 ;
; ; ; ;
; Logic element usage by number of LUT inputs ; ; ;
; -- 4 input functions ; 0 ; 0 ;
; -- synchronous clear/load mode ; 0 ; 0 ;
; -- asynchronous clear/load mode ; 0 ; 0 ;
; ; ; ;
-; Total registers ; 141 / 6030 ( 2 % ) ; 0 / 6030 ( 0 % ) ;
+; Total registers ; 215 / 6030 ( 3 % ) ; 0 / 6030 ( 0 % ) ;
; Virtual pins ; 0 ; 0 ;
-; I/O pins ; 2 ; 0 ;
+; I/O pins ; 3 ; 0 ;
; DSP block 9-bit elements ; 0 ; 0 ;
; Total memory bits ; 512 ; 0 ;
; Total RAM block bits ; 9216 ; 0 ;
; -- Registered Output Connections ; 0 ; 0 ;
; ; ; ;
; Internal Connections ; ; ;
-; -- Total Connections ; 1572 ; 0 ;
-; -- Registered Connections ; 590 ; 0 ;
+; -- Total Connections ; 4343 ; 0 ;
+; -- Registered Connections ; 813 ; 0 ;
; ; ; ;
; External Connections ; ; ;
; -- Top ; 0 ; 0 ;
; -- hard_block:auto_generated_inst ; 0 ; 0 ;
; ; ; ;
; Partition Interface ; ; ;
-; -- Input Ports ; 1 ; 0 ;
+; -- Input Ports ; 2 ; 0 ;
; -- Output Ports ; 1 ; 0 ;
; -- Bidir Ports ; 0 ; 0 ;
; ; ; ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
-; sys_clk ; 152 ; 3 ; 53 ; 15 ; 2 ; 143 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+; sys_clk ; 152 ; 3 ; 53 ; 15 ; 2 ; 217 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+; sys_res ; 42 ; 1 ; 0 ; 6 ; 0 ; 205 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVCMOS ; Off ; User ;
+---------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+
+----------+----------------+---------------+--------------+
; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ;
+----------+----------------+---------------+--------------+
-; 1 ; 2 / 44 ( 5 % ) ; 3.3V ; -- ;
+; 1 ; 3 / 44 ( 7 % ) ; 3.3V ; -- ;
; 2 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ;
; 3 ; 2 / 45 ( 4 % ) ; 3.3V ; -- ;
; 4 ; 0 / 42 ( 0 % ) ; 3.3V ; -- ;
; 39 ; 41 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 40 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ;
; 41 ; 52 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
-; 42 ; 53 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+; 42 ; 53 ; 1 ; sys_res ; input ; 3.3-V LVCMOS ; ; Row I/O ; Y ; no ; Off ;
; 43 ; 54 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 44 ; 55 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
; 45 ; 56 ; 1 ; RESERVED_INPUT ; ; ; ; Row I/O ; ; no ; Off ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; M4Ks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
-; |core_top ; 398 (1) ; 141 ; 512 ; 2 ; 2 ; 0 ; 257 (1) ; 12 (0) ; 129 (0) ; 104 (0) ; 35 (0) ; |core_top ; ;
-; |decode_stage:decode_st| ; 43 (42) ; 42 ; 512 ; 2 ; 0 ; 0 ; 1 (0) ; 1 (1) ; 41 (41) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st ; ;
-; |decoder:decoder_inst| ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
+; |core_top ; 1056 (1) ; 215 ; 512 ; 2 ; 3 ; 0 ; 841 (1) ; 0 (0) ; 215 (0) ; 214 (0) ; 77 (0) ; |core_top ; ;
+; |decode_stage:decode_st| ; 103 (96) ; 72 ; 512 ; 2 ; 0 ; 0 ; 31 (24) ; 0 (0) ; 72 (72) ; 11 (11) ; 5 (5) ; |core_top|decode_stage:decode_st ; ;
+; |decoder:decoder_inst| ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|decoder:decoder_inst ; ;
; |r2_w_ram:register_ram| ; 0 (0) ; 0 ; 512 ; 2 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram ; ;
; |altsyncram:ram_rtl_0| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated ; ;
; |altsyncram:ram_rtl_1| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1 ; ;
; |altsyncram_emk1:auto_generated| ; 0 (0) ; 0 ; 256 ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated ; ;
-; |execute_stage:exec_st| ; 191 (129) ; 34 ; 0 ; 0 ; 0 ; 0 ; 157 (95) ; 0 (0) ; 34 (34) ; 61 (0) ; 35 (35) ; |core_top|execute_stage:exec_st ; ;
-; |alu:alu_inst| ; 62 (30) ; 0 ; 0 ; 0 ; 0 ; 0 ; 62 (30) ; 0 (0) ; 0 (0) ; 61 (29) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
-; |exec_op:add_inst| ; 32 (32) ; 0 ; 0 ; 0 ; 0 ; 0 ; 32 (32) ; 0 (0) ; 0 (0) ; 32 (32) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
-; |fetch_stage:fetch_st| ; 28 (22) ; 14 ; 0 ; 0 ; 0 ; 0 ; 14 (11) ; 11 (11) ; 3 (0) ; 11 (11) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
-; |r_w_ram:instruction_ram| ; 6 (6) ; 3 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
-; |writeback_stage:writeback_st| ; 135 (28) ; 51 ; 0 ; 0 ; 0 ; 0 ; 84 (26) ; 0 (0) ; 51 (2) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st ; ;
-; |extension_uart:uart| ; 107 (13) ; 49 ; 0 ; 0 ; 0 ; 0 ; 58 (3) ; 0 (0) ; 49 (10) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
+; |execute_stage:exec_st| ; 755 (145) ; 67 ; 0 ; 0 ; 0 ; 0 ; 688 (109) ; 0 (0) ; 67 (36) ; 171 (0) ; 71 (40) ; |core_top|execute_stage:exec_st ; ;
+; |alu:alu_inst| ; 545 (224) ; 0 ; 0 ; 0 ; 0 ; 0 ; 545 (224) ; 0 (0) ; 0 (0) ; 141 (43) ; 31 (31) ; |core_top|execute_stage:exec_st|alu:alu_inst ; ;
+; |exec_op:add_inst| ; 100 (100) ; 0 ; 0 ; 0 ; 0 ; 0 ; 100 (100) ; 0 (0) ; 0 (0) ; 98 (98) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:add_inst ; ;
+; |exec_op:or_inst| ; 13 (13) ; 0 ; 0 ; 0 ; 0 ; 0 ; 13 (13) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:or_inst ; ;
+; |exec_op:shift_inst| ; 208 (208) ; 0 ; 0 ; 0 ; 0 ; 0 ; 208 (208) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |core_top|execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst ; ;
+; |extension_gpm:gpmp_inst| ; 65 (65) ; 31 ; 0 ; 0 ; 0 ; 0 ; 34 (34) ; 0 (0) ; 31 (31) ; 30 (30) ; 0 (0) ; |core_top|execute_stage:exec_st|extension_gpm:gpmp_inst ; ;
+; |fetch_stage:fetch_st| ; 33 (24) ; 17 ; 0 ; 0 ; 0 ; 0 ; 16 (13) ; 0 (0) ; 17 (11) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st ; ;
+; |r_w_ram:instruction_ram| ; 9 (9) ; 6 ; 0 ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|fetch_stage:fetch_st|r_w_ram:instruction_ram ; ;
+; |writeback_stage:writeback_st| ; 164 (52) ; 59 ; 0 ; 0 ; 0 ; 0 ; 105 (48) ; 0 (0) ; 59 (4) ; 32 (0) ; 1 (1) ; |core_top|writeback_stage:writeback_st ; ;
+; |extension_uart:uart| ; 106 (12) ; 49 ; 0 ; 0 ; 0 ; 0 ; 57 (2) ; 0 (0) ; 49 (10) ; 32 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart ; ;
; |rs232_tx:rs232_tx_inst| ; 94 (94) ; 39 ; 0 ; 0 ; 0 ; 0 ; 55 (55) ; 0 (0) ; 39 (39) ; 32 (32) ; 0 (0) ; |core_top|writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst ; ;
+; |r_w_ram:data_ram| ; 6 (6) ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 6 (6) ; 0 (0) ; 0 (0) ; |core_top|writeback_stage:writeback_st|r_w_ram:data_ram ; ;
+----------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------+----------+---------------+---------------+-----------------------+-----+
; bus_tx ; Output ; -- ; -- ; -- ; -- ;
; sys_clk ; Input ; OFF ; OFF ; -- ; -- ;
+; sys_res ; Input ; OFF ; ON ; -- ; -- ;
+---------+----------+---------------+---------------+-----------------------+-----+
-+---------------------------------------------------+
-; Pad To Core Delay Chain Fanout ;
-+---------------------+-------------------+---------+
-; Source Pin / Fanout ; Pad To Core Index ; Setting ;
-+---------------------+-------------------+---------+
-; sys_clk ; ; ;
-+---------------------+-------------------+---------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Control Signals ;
-+--------------------------------------------------------------------------------------+---------------+---------+--------------+--------+----------------------+------------------+
-; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
-+--------------------------------------------------------------------------------------+---------------+---------+--------------+--------+----------------------+------------------+
-; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; LC_X30_Y13_N4 ; 56 ; Sync. load ; no ; -- ; -- ;
-; execute_stage:exec_st|reg.wr_en ; LC_X31_Y16_N0 ; 7 ; Write enable ; no ; -- ; -- ;
-; sys_clk ; PIN_152 ; 143 ; Clock ; yes ; Global Clock ; GCLK7 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X39_Y14_N4 ; 5 ; Clock enable ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X39_Y14_N3 ; 35 ; Sync. clear ; no ; -- ; -- ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1 ; LC_X28_Y11_N8 ; 8 ; Clock enable ; no ; -- ; -- ;
-+--------------------------------------------------------------------------------------+---------------+---------+--------------+--------+----------------------+------------------+
++---------------------------------------------------------------------------------------------------------------------------+
+; Pad To Core Delay Chain Fanout ;
++---------------------------------------------------------------------------------------------+-------------------+---------+
+; Source Pin / Fanout ; Pad To Core Index ; Setting ;
++---------------------------------------------------------------------------------------------+-------------------+---------+
+; sys_clk ; ; ;
+; sys_res ; ; ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[4] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[6] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[29] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[31] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[30] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[29] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[28] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[27] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[26] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[25] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[24] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[23] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[22] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[21] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[20] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[19] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[18] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[17] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[16] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[15] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[14] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[13] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[12] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[11] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[10] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[9] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[8] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[7] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[6] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[5] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[4] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[3] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[2] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg2 ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.wr_en ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.dmem_en ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.alu_jump ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.address[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][1] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][7] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][2] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][3] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][4] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][5] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][6] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][8] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][9] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][10] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.brpr ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.condition[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0 ; 1 ; ON ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[3] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[1] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w1_st_co[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[0] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[5] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.daddr[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg1 ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[9] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[8] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[17] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[15] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[16] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[14] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[13] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[11] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[12] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[10] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.brpr ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[6] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[21] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[22] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[23] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[24] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[25] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[26] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[27] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[28] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[31] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[18] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[20] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.result[19] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr_nxt[3]~3 ; 1 ; ON ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.displacement[1] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.carry ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_detail[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[0] ; 0 ; OFF ;
+; - writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; 1 ; ON ;
+; - decode_stage:decode_st|rtw_rec.immediate[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.immediate[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.imm_set ; 0 ; OFF ;
+; - writeback_stage:writeback_st|wb_reg.dmem_write_en ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr2[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[5] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[8] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[9] ; 0 ; OFF ;
+; - execute_stage:exec_st|reg.res_addr[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[10] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[11] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[0] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[12] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[1] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[13] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[2] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[14] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[3] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[15] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[4] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[16] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[5] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[17] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[6] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[18] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[7] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[19] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[8] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[20] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[9] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[21] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.prog_cnt[10] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[22] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[23] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[24] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[25] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[26] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[27] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[28] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[29] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[30] ; 0 ; OFF ;
+; - decode_stage:decode_st|rtw_rec.rtw_reg[31] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[10] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[9] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[0] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[8] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[1] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[7] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[2] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[6] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[3] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[5] ; 0 ; OFF ;
+; - fetch_stage:fetch_st|instr_r_addr[4] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][19] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][22] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][20] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][23] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][24] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][21] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][25] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][26] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][27] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][12] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][28] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][11] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][14] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][18] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][13] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][29] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][16] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][15] ; 0 ; OFF ;
+; - execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][17] ; 0 ; OFF ;
+; - decode_stage:decode_st|dec_op_inst.saddr1[2] ; 0 ; OFF ;
++---------------------------------------------------------------------------------------------+-------------------+---------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Control Signals ;
++--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ;
++--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; LC_X27_Y17_N9 ; 58 ; Sync. load ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|calc~0 ; LC_X36_Y17_N6 ; 32 ; Sync. clear, Sync. load ; no ; -- ; -- ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; LC_X29_Y15_N2 ; 30 ; Clock enable ; no ; -- ; -- ;
+; execute_stage:exec_st|reg.result[1]~9 ; LC_X27_Y16_N4 ; 12 ; Sync. load ; no ; -- ; -- ;
+; sys_clk ; PIN_152 ; 217 ; Clock ; yes ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 205 ; Async. clear, Async. load, Clock enable ; yes ; Global Clock ; GCLK3 ;
+; writeback_stage:writeback_st|Mux9~0 ; LC_X26_Y19_N7 ; 7 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|bus_tx_int~0 ; LC_X40_Y20_N6 ; 5 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; LC_X40_Y19_N5 ; 35 ; Sync. clear ; no ; -- ; -- ;
+; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0 ; LC_X27_Y19_N6 ; 8 ; Clock enable ; no ; -- ; -- ;
+; writeback_stage:writeback_st|reg_we~0 ; LC_X31_Y18_N0 ; 8 ; Write enable ; no ; -- ; -- ;
++--------------------------------------------------------------------------------------+---------------+---------+-----------------------------------------+--------+----------------------+------------------+
+------------------------------------------------------------------------+
+---------+----------+---------+----------------------+------------------+
; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ;
+---------+----------+---------+----------------------+------------------+
-; sys_clk ; PIN_152 ; 143 ; Global Clock ; GCLK7 ;
+; sys_clk ; PIN_152 ; 217 ; Global Clock ; GCLK7 ;
+; sys_res ; PIN_42 ; 205 ; Global Clock ; GCLK3 ;
+---------+----------+---------+----------------------+------------------+
+-----------------------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+-----------------------------------------------------------------------------------+---------+
-; decode_stage:decode_st|rtw_rec.immediate[3] ; 66 ;
-; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 56 ;
+; execute_stage:exec_st|alu:alu_inst|Selector76~0 ; 115 ;
+; execute_stage:exec_st|right_operand[0]~10 ; 89 ;
+; execute_stage:exec_st|right_operand[1]~6 ; 77 ;
+; execute_stage:exec_st|right_operand[2]~4 ; 63 ;
+; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ; 58 ;
+; execute_stage:exec_st|alu:alu_inst|Selector53~0 ; 53 ;
+; decode_stage:decode_st|dec_op_inst.op_detail[3] ; 49 ;
+; execute_stage:exec_st|right_operand[3]~8 ; 48 ;
+; decode_stage:decode_st|dec_op_inst.op_detail[2] ; 41 ;
+; execute_stage:exec_st|left_operand[13]~1 ; 40 ;
+; execute_stage:exec_st|right_operand[14]~1 ; 38 ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[26] ; 37 ;
+; execute_stage:exec_st|right_operand[14]~2 ; 37 ;
+; writeback_stage:writeback_st|wb_reg.dmem_en ; 35 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; 35 ;
+; writeback_stage:writeback_st|wb_reg.dmem_write_en ; 34 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|Equal0~10 ; 34 ;
-; execute_stage:exec_st|left_operand[28]~1 ; 32 ;
+; execute_stage:exec_st|alu:alu_inst|calc~0 ; 32 ;
; decode_stage:decode_st|rtw_rec.rtw_reg1 ; 32 ;
-; execute_stage:exec_st|right_operand[6]~1 ; 30 ;
-; decode_stage:decode_st|rtw_rec.rtw_reg2 ; 29 ;
+; execute_stage:exec_st|alu:alu_inst|pwr_en ; 30 ;
+; execute_stage:exec_st|reg.result[11]~12 ; 29 ;
+; execute_stage:exec_st|alu:alu_inst|pinc~0 ; 29 ;
+; writeback_stage:writeback_st|jump ; 25 ;
+; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ; 25 ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[25] ; 24 ;
+; execute_stage:exec_st|reg.result[11]~13 ; 23 ;
+; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; 23 ;
+; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ; 21 ;
+; decode_stage:decode_st|decoder:decoder_inst|instr_s~5 ; 15 ;
+; decode_stage:decode_st|rtw_rec.imm_set ; 15 ;
+; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ; 13 ;
+; execute_stage:exec_st|reg.result[1]~9 ; 12 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; 12 ;
; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; 10 ;
-; writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1 ; 8 ;
-; execute_stage:exec_st|reg.res_addr[2] ; 8 ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[21] ; 7 ;
-; execute_stage:exec_st|right_operand[6]~5 ; 7 ;
-; execute_stage:exec_st|reg.wr_en ; 7 ;
-; writeback_stage:writeback_st|wb_reg.address[0] ; 7 ;
-; writeback_stage:writeback_st|wb_reg.address[1] ; 7 ;
-; fetch_stage:fetch_st|r_w_ram:instruction_ram|data_out[27] ; 6 ;
-; execute_stage:exec_st|right_operand[6]~6 ; 6 ;
-; execute_stage:exec_st|reg.result[3] ; 6 ;
-; execute_stage:exec_st|reg.result[1] ; 6 ;
-; writeback_stage:writeback_st|Equal0~24 ; 6 ;
-; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; 6 ;
-; ~GND ; 5 ;
-; execute_stage:exec_st|reg.result[27] ; 5 ;
-; execute_stage:exec_st|reg.result[26] ; 5 ;
-; execute_stage:exec_st|reg.result[25] ; 5 ;
-; execute_stage:exec_st|reg.result[24] ; 5 ;
-; execute_stage:exec_st|reg.result[23] ; 5 ;
-; execute_stage:exec_st|reg.result[22] ; 5 ;
-; execute_stage:exec_st|reg.result[21] ; 5 ;
-; execute_stage:exec_st|reg.result[20] ; 5 ;
-; execute_stage:exec_st|reg.result[19] ; 5 ;
-; execute_stage:exec_st|reg.result[18] ; 5 ;
-; execute_stage:exec_st|reg.result[17] ; 5 ;
-; execute_stage:exec_st|reg.result[16] ; 5 ;
-; execute_stage:exec_st|reg.result[15] ; 5 ;
-; execute_stage:exec_st|reg.result[14] ; 5 ;
-; execute_stage:exec_st|reg.result[13] ; 5 ;
-; execute_stage:exec_st|reg.result[11] ; 5 ;
-; execute_stage:exec_st|reg.result[10] ; 5 ;
-; execute_stage:exec_st|reg.result[9] ; 5 ;
-; execute_stage:exec_st|reg.result[8] ; 5 ;
-; execute_stage:exec_st|reg.result[12] ; 5 ;
-; execute_stage:exec_st|reg.result[31] ; 5 ;
-; execute_stage:exec_st|reg.result[30] ; 5 ;
-; execute_stage:exec_st|reg.result[29] ; 5 ;
-; execute_stage:exec_st|reg.result[28] ; 5 ;
-; execute_stage:exec_st|reg.result[4] ; 5 ;
-; execute_stage:exec_st|reg.result[7] ; 5 ;
+; execute_stage:exec_st|alu:alu_inst|exec_op:shift_inst|tmp_sb~0 ; 9 ;
+; execute_stage:exec_st|left_operand[30]~56 ; 9 ;
+; execute_stage:exec_st|left_operand[29]~54 ; 9 ;
+; execute_stage:exec_st|left_operand[28]~52 ; 9 ;
+; execute_stage:exec_st|reg.res_addr[2] ; 9 ;
+; execute_stage:exec_st|reg.result[6]~21 ; 8 ;
+; execute_stage:exec_st|reg.result[25]~14 ; 8 ;
+; execute_stage:exec_st|alu:alu_inst|Selector76~1 ; 8 ;
+; execute_stage:exec_st|left_operand[27]~50 ; 8 ;
+; execute_stage:exec_st|left_operand[26]~48 ; 8 ;
+; execute_stage:exec_st|alu:alu_inst|Selector97~0 ; 8 ;
+; execute_stage:exec_st|left_operand[12]~34 ; 8 ;
+; execute_stage:exec_st|left_operand[11]~32 ; 8 ;
+; execute_stage:exec_st|alu:alu_inst|Selector98~0 ; 8 ;
+; execute_stage:exec_st|alu:alu_inst|Selector107~0 ; 8 ;
+; execute_stage:exec_st|right_operand[14]~13 ; 8 ;
+-----------------------------------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
; Name ; Type ; Mode ; Clock Mode ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Port A Input Registers ; Port A Output Registers ; Port B Input Registers ; Port B Output Registers ; Size ; Implementation Port A Depth ; Implementation Port A Width ; Implementation Port B Depth ; Implementation Port B Width ; Implementation Bits ; M4Ks ; MIF ; Location ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y16 ;
-; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y15 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y18 ;
+; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_1|altsyncram_emk1:auto_generated|ALTSYNCRAM ; AUTO ; Simple Dual Port ; Single Clock ; 16 ; 32 ; 16 ; 32 ; yes ; no ; yes ; no ; 512 ; 8 ; 32 ; 8 ; 32 ; 256 ; 1 ; db/dt.ram0_r2_w_ram_8e30dd1c.hdl.mif ; M4K_X33_Y19 ;
+-------------------------------------------------------------------------------------------------------------+------+------------------+--------------+--------------+--------------+--------------+--------------+------------------------+-------------------------+------------------------+-------------------------+------+-----------------------------+-----------------------------+-----------------------------+-----------------------------+---------------------+------+--------------------------------------+-------------+
Note: Fitter may spread logical memories into multiple blocks to improve timing. The actual required RAM blocks can be found in the Fitter Resource Usage section.
-+----------------------------------------------------+
-; Interconnect Usage Summary ;
-+----------------------------+-----------------------+
-; Interconnect Resource Type ; Usage ;
-+----------------------------+-----------------------+
-; C4s ; 433 / 30,600 ( 1 % ) ;
-; Direct links ; 43 / 43,552 ( < 1 % ) ;
-; Global clocks ; 1 / 8 ( 13 % ) ;
-; LAB clocks ; 12 / 312 ( 4 % ) ;
-; LUT chains ; 46 / 10,854 ( < 1 % ) ;
-; Local interconnects ; 653 / 43,552 ( 1 % ) ;
-; M4K buffers ; 64 / 1,872 ( 3 % ) ;
-; R4s ; 439 / 28,560 ( 2 % ) ;
-+----------------------------+-----------------------+
-
-
-+---------------------------------------------------------------------------+
-; LAB Logic Elements ;
-+--------------------------------------------+------------------------------+
-; Number of Logic Elements (Average = 8.29) ; Number of LABs (Total = 48) ;
-+--------------------------------------------+------------------------------+
-; 1 ; 7 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 1 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 2 ;
-; 8 ; 0 ;
-; 9 ; 0 ;
-; 10 ; 37 ;
-+--------------------------------------------+------------------------------+
-
-
-+-------------------------------------------------------------------+
-; LAB-wide Signals ;
-+------------------------------------+------------------------------+
-; LAB-wide Signals (Average = 0.92) ; Number of LABs (Total = 48) ;
-+------------------------------------+------------------------------+
-; 1 Clock ; 39 ;
-; 1 Clock enable ; 2 ;
-; 1 Sync. load ; 2 ;
-; 2 Clock enables ; 1 ;
-+------------------------------------+------------------------------+
++-----------------------------------------------------+
+; Interconnect Usage Summary ;
++----------------------------+------------------------+
+; Interconnect Resource Type ; Usage ;
++----------------------------+------------------------+
+; C4s ; 1,397 / 30,600 ( 5 % ) ;
+; Direct links ; 137 / 43,552 ( < 1 % ) ;
+; Global clocks ; 2 / 8 ( 25 % ) ;
+; LAB clocks ; 32 / 312 ( 10 % ) ;
+; LUT chains ; 146 / 10,854 ( 1 % ) ;
+; Local interconnects ; 1,899 / 43,552 ( 4 % ) ;
+; M4K buffers ; 64 / 1,872 ( 3 % ) ;
+; R4s ; 1,532 / 28,560 ( 5 % ) ;
++----------------------------+------------------------+
+----------------------------------------------------------------------------+
-; LAB Signals Sourced ;
-+---------------------------------------------+------------------------------+
-; Number of Signals Sourced (Average = 9.10) ; Number of LABs (Total = 48) ;
-+---------------------------------------------+------------------------------+
-; 0 ; 0 ;
-; 1 ; 7 ;
-; 2 ; 0 ;
-; 3 ; 1 ;
-; 4 ; 1 ;
-; 5 ; 0 ;
-; 6 ; 0 ;
-; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 0 ;
-; 10 ; 18 ;
-; 11 ; 4 ;
-; 12 ; 13 ;
-; 13 ; 1 ;
-; 14 ; 0 ;
-; 15 ; 1 ;
-+---------------------------------------------+------------------------------+
-
-
-+--------------------------------------------------------------------------------+
-; LAB Signals Sourced Out ;
-+-------------------------------------------------+------------------------------+
-; Number of Signals Sourced Out (Average = 6.02) ; Number of LABs (Total = 48) ;
-+-------------------------------------------------+------------------------------+
-; 0 ; 0 ;
-; 1 ; 7 ;
-; 2 ; 1 ;
-; 3 ; 3 ;
-; 4 ; 3 ;
-; 5 ; 4 ;
-; 6 ; 14 ;
-; 7 ; 1 ;
-; 8 ; 1 ;
-; 9 ; 3 ;
-; 10 ; 10 ;
-; 11 ; 0 ;
-; 12 ; 0 ;
-; 13 ; 1 ;
-+-------------------------------------------------+------------------------------+
+; LAB Logic Elements ;
++--------------------------------------------+-------------------------------+
+; Number of Logic Elements (Average = 9.26) ; Number of LABs (Total = 114) ;
++--------------------------------------------+-------------------------------+
+; 1 ; 6 ;
+; 2 ; 1 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 2 ;
+; 6 ; 0 ;
+; 7 ; 1 ;
+; 8 ; 0 ;
+; 9 ; 2 ;
+; 10 ; 101 ;
++--------------------------------------------+-------------------------------+
+
+
++--------------------------------------------------------------------+
+; LAB-wide Signals ;
++------------------------------------+-------------------------------+
+; LAB-wide Signals (Average = 1.44) ; Number of LABs (Total = 114) ;
++------------------------------------+-------------------------------+
+; 1 Async. clear ; 69 ;
+; 1 Async. load ; 2 ;
+; 1 Clock ; 72 ;
+; 1 Clock enable ; 13 ;
+; 1 Sync. clear ; 3 ;
+; 1 Sync. load ; 5 ;
++------------------------------------+-------------------------------+
+-----------------------------------------------------------------------------+
-; LAB Distinct Inputs ;
-+----------------------------------------------+------------------------------+
-; Number of Distinct Inputs (Average = 12.08) ; Number of LABs (Total = 48) ;
-+----------------------------------------------+------------------------------+
-; 0 ; 0 ;
-; 1 ; 0 ;
-; 2 ; 7 ;
-; 3 ; 1 ;
-; 4 ; 0 ;
-; 5 ; 1 ;
-; 6 ; 0 ;
-; 7 ; 0 ;
-; 8 ; 2 ;
-; 9 ; 1 ;
-; 10 ; 1 ;
-; 11 ; 4 ;
-; 12 ; 0 ;
-; 13 ; 12 ;
-; 14 ; 2 ;
-; 15 ; 4 ;
-; 16 ; 0 ;
-; 17 ; 3 ;
-; 18 ; 0 ;
-; 19 ; 1 ;
-; 20 ; 3 ;
-; 21 ; 5 ;
-+----------------------------------------------+------------------------------+
+; LAB Signals Sourced ;
++---------------------------------------------+-------------------------------+
+; Number of Signals Sourced (Average = 9.97) ; Number of LABs (Total = 114) ;
++---------------------------------------------+-------------------------------+
+; 0 ; 0 ;
+; 1 ; 6 ;
+; 2 ; 1 ;
+; 3 ; 1 ;
+; 4 ; 0 ;
+; 5 ; 2 ;
+; 6 ; 0 ;
+; 7 ; 0 ;
+; 8 ; 1 ;
+; 9 ; 2 ;
+; 10 ; 60 ;
+; 11 ; 21 ;
+; 12 ; 7 ;
+; 13 ; 7 ;
+; 14 ; 6 ;
++---------------------------------------------+-------------------------------+
+
+
++---------------------------------------------------------------------------------+
+; LAB Signals Sourced Out ;
++-------------------------------------------------+-------------------------------+
+; Number of Signals Sourced Out (Average = 6.84) ; Number of LABs (Total = 114) ;
++-------------------------------------------------+-------------------------------+
+; 0 ; 0 ;
+; 1 ; 6 ;
+; 2 ; 1 ;
+; 3 ; 7 ;
+; 4 ; 7 ;
+; 5 ; 14 ;
+; 6 ; 15 ;
+; 7 ; 14 ;
+; 8 ; 17 ;
+; 9 ; 10 ;
+; 10 ; 18 ;
+; 11 ; 2 ;
+; 12 ; 2 ;
+; 13 ; 1 ;
++-------------------------------------------------+-------------------------------+
+
+
++------------------------------------------------------------------------------+
+; LAB Distinct Inputs ;
++----------------------------------------------+-------------------------------+
+; Number of Distinct Inputs (Average = 16.04) ; Number of LABs (Total = 114) ;
++----------------------------------------------+-------------------------------+
+; 0 ; 0 ;
+; 1 ; 0 ;
+; 2 ; 0 ;
+; 3 ; 3 ;
+; 4 ; 1 ;
+; 5 ; 2 ;
+; 6 ; 1 ;
+; 7 ; 0 ;
+; 8 ; 2 ;
+; 9 ; 0 ;
+; 10 ; 5 ;
+; 11 ; 8 ;
+; 12 ; 7 ;
+; 13 ; 3 ;
+; 14 ; 9 ;
+; 15 ; 5 ;
+; 16 ; 5 ;
+; 17 ; 6 ;
+; 18 ; 7 ;
+; 19 ; 4 ;
+; 20 ; 18 ;
+; 21 ; 16 ;
+; 22 ; 11 ;
++----------------------------------------------+-------------------------------+
+--------------------------------------------------------------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Thu Dec 16 16:54:47 2010
+ Info: Processing started: Fri Dec 17 10:10:15 2010
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off dt -c dt
Info: Selected device EP1C12Q240C8 for design "dt"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Completed User Assigned Global Signals Promotion Operation
Info: DQS I/O pins require 0 global routing resources
Info: Automatically promoted signal "sys_clk" to use Global clock in PIN 152
+Info: Automatically promoted some destinations of signal "sys_res" to use Global clock
+ Info: Destination "execute_stage:exec_st|alu:alu_inst|\calc:cond_met~0" may be non-global or may not use global clock
+ Info: Destination "writeback_stage:writeback_st|extension_uart:uart|new_tx_data" may be non-global or may not use global clock
+ Info: Destination "fetch_stage:fetch_st|instr_r_addr_nxt[3]~3" may be non-global or may not use global clock
+Info: Pin "sys_res" drives global clock, but is not placed in a dedicated clock pin position
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Extra Info: Started Fast Input/Output/OE register processing
Info: Finished moving registers into I/O cells, LUTs, and RAM blocks
Info: Finished register packing
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
-Info: Fitter preparation operations ending: elapsed time is 00:00:01
+Info: Fitter preparation operations ending: elapsed time is 00:00:02
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
-Info: Fitter placement operations ending: elapsed time is 00:00:01
-Info: Estimated most critical path is memory to register delay of 18.381 ns
- Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y16; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3~portb_address_reg2'
- Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y16; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3'
- Info: 3: + IC(1.233 ns) + CELL(0.442 ns) = 5.992 ns; Loc. = LAB_X32_Y14; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[3]~61'
- Info: 4: + IC(0.757 ns) + CELL(0.590 ns) = 7.339 ns; Loc. = LAB_X31_Y15; Fanout = 6; COMB Node = 'execute_stage:exec_st|left_operand[3]~62'
- Info: 5: + IC(1.395 ns) + CELL(0.575 ns) = 9.309 ns; Loc. = LAB_X28_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~142COUT1_190'
- Info: 6: + IC(0.000 ns) + CELL(0.080 ns) = 9.389 ns; Loc. = LAB_X28_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~27COUT1_192'
- Info: 7: + IC(0.000 ns) + CELL(0.608 ns) = 9.997 ns; Loc. = LAB_X28_Y14; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add2~30'
- Info: 8: + IC(1.387 ns) + CELL(0.292 ns) = 11.676 ns; Loc. = LAB_X30_Y12; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~4'
- Info: 9: + IC(0.900 ns) + CELL(0.442 ns) = 13.018 ns; Loc. = LAB_X30_Y13; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~7'
- Info: 10: + IC(0.752 ns) + CELL(0.590 ns) = 14.360 ns; Loc. = LAB_X29_Y12; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~23'
- Info: 11: + IC(0.900 ns) + CELL(0.442 ns) = 15.702 ns; Loc. = LAB_X28_Y11; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~1'
- Info: 12: + IC(1.812 ns) + CELL(0.867 ns) = 18.381 ns; Loc. = LAB_X36_Y14; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
- Info: Total cell delay = 9.245 ns ( 50.30 % )
- Info: Total interconnect delay = 9.136 ns ( 49.70 % )
+Info: Fitter placement operations ending: elapsed time is 00:00:02
+Info: Estimated most critical path is memory to register delay of 20.863 ns
+ Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3~portb_address_reg2'
+ Info: 2: + IC(0.000 ns) + CELL(4.317 ns) = 4.317 ns; Loc. = M4K_X33_Y18; Fanout = 1; MEM Node = 'decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_0|altsyncram_emk1:auto_generated|ram_block1a3'
+ Info: 3: + IC(1.586 ns) + CELL(0.442 ns) = 6.345 ns; Loc. = LAB_X28_Y22; Fanout = 1; COMB Node = 'execute_stage:exec_st|left_operand[3]~19'
+ Info: 4: + IC(0.063 ns) + CELL(0.590 ns) = 6.998 ns; Loc. = LAB_X28_Y22; Fanout = 4; COMB Node = 'execute_stage:exec_st|left_operand[3]~20'
+ Info: 5: + IC(0.117 ns) + CELL(0.590 ns) = 7.705 ns; Loc. = LAB_X28_Y22; Fanout = 8; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector104~0'
+ Info: 6: + IC(0.995 ns) + CELL(0.575 ns) = 9.275 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~2COUT1_196'
+ Info: 7: + IC(0.000 ns) + CELL(0.080 ns) = 9.355 ns; Loc. = LAB_X31_Y22; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~12COUT1_198'
+ Info: 8: + IC(0.000 ns) + CELL(0.258 ns) = 9.613 ns; Loc. = LAB_X31_Y22; Fanout = 6; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~17'
+ Info: 9: + IC(0.000 ns) + CELL(0.679 ns) = 10.292 ns; Loc. = LAB_X31_Y21; Fanout = 3; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|Add1~20'
+ Info: 10: + IC(0.771 ns) + CELL(0.432 ns) = 11.495 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[6]~22COUT1_195'
+ Info: 11: + IC(0.000 ns) + CELL(0.080 ns) = 11.575 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[7]~27COUT1_197'
+ Info: 12: + IC(0.000 ns) + CELL(0.080 ns) = 11.655 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[8]~32COUT1_199'
+ Info: 13: + IC(0.000 ns) + CELL(0.608 ns) = 12.263 ns; Loc. = LAB_X30_Y21; Fanout = 2; COMB Node = 'execute_stage:exec_st|alu:alu_inst|exec_op:add_inst|alu_result.result[9]~5'
+ Info: 14: + IC(1.264 ns) + CELL(0.114 ns) = 13.641 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector65~0'
+ Info: 15: + IC(0.361 ns) + CELL(0.292 ns) = 14.294 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'execute_stage:exec_st|alu:alu_inst|Selector65~1'
+ Info: 16: + IC(0.063 ns) + CELL(0.590 ns) = 14.947 ns; Loc. = LAB_X31_Y17; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~0'
+ Info: 17: + IC(0.303 ns) + CELL(0.590 ns) = 15.840 ns; Loc. = LAB_X30_Y17; Fanout = 7; COMB Node = 'writeback_stage:writeback_st|Equal0~5'
+ Info: 18: + IC(1.093 ns) + CELL(0.590 ns) = 17.523 ns; Loc. = LAB_X27_Y19; Fanout = 1; COMB Node = 'writeback_stage:writeback_st|Equal0~8'
+ Info: 19: + IC(0.063 ns) + CELL(0.590 ns) = 18.176 ns; Loc. = LAB_X27_Y19; Fanout = 5; COMB Node = 'writeback_stage:writeback_st|Equal0~12'
+ Info: 20: + IC(0.211 ns) + CELL(0.442 ns) = 18.829 ns; Loc. = LAB_X27_Y19; Fanout = 8; COMB Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]~0'
+ Info: 21: + IC(1.167 ns) + CELL(0.867 ns) = 20.863 ns; Loc. = LAB_X28_Y21; Fanout = 1; REG Node = 'writeback_stage:writeback_st|extension_uart:uart|w3_uart_send[7]'
+ Info: Total cell delay = 12.806 ns ( 61.38 % )
+ Info: Total interconnect delay = 8.057 ns ( 38.62 % )
Info: Fitter routing operations beginning
-Info: Router estimated average interconnect usage is 1% of the available device resources
- Info: Router estimated peak interconnect usage is 3% of the available device resources in the region that extends from location X21_Y14 to location X31_Y27
-Info: Fitter routing operations ending: elapsed time is 00:00:01
+Info: Router estimated average interconnect usage is 4% of the available device resources
+ Info: Router estimated peak interconnect usage is 25% of the available device resources in the region that extends from location X21_Y14 to location X31_Y27
+Info: Fitter routing operations ending: elapsed time is 00:00:04
Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time.
Info: Optimizations that may affect the design's routability were skipped
Info: Optimizations that may affect the design's timing were skipped
Info: Completed Auto Delay Chain Operation
Info: Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements.
Info: Quartus II Fitter was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 266 megabytes
- Info: Processing ended: Thu Dec 16 16:54:58 2010
- Info: Elapsed time: 00:00:11
- Info: Total CPU time (on all processors): 00:00:11
+ Info: Peak virtual memory: 269 megabytes
+ Info: Processing ended: Fri Dec 17 10:10:34 2010
+ Info: Elapsed time: 00:00:19
+ Info: Total CPU time (on all processors): 00:00:19
projects / calu.git / blobdiff