spartan3e: BRAM gehaxe. lesbarer und wird auch richtig(er) instanziert

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index a4d30f68d535f108d39bb58c490176808e26fd3c..a031207123e2836ec47551455ac1df7391623ae4 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -9,6 +9,7 @@ use work.mem_pkg.all;
 use work.extension_pkg.all;
 use work.extension_uart_pkg.all;
 use work.extension_7seg_pkg.all;
+use work.extension_imp_pkg.all;
 
 architecture behav of writeback_stage is
 
@@ -17,8 +18,8 @@ signal data_addr : word_t;
 
 signal wb_reg, wb_reg_nxt : writeback_rec;
 
-signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int :  extmod_rec;
-signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out : gp_register_t;
+signal ext_uart,ext_timer,ext_gpmp,ext_7seg,ext_int,ext_imp :  extmod_rec;
+signal ext_uart_out, ext_timer_out, ext_gpmp_out, ext_int_out,ext_imp_out : gp_register_t;
 
 --signal int_req : interrupt_t;
 signal uart_int : std_logic;
@@ -33,6 +34,23 @@ begin
        ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
        ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
 
+       spartan3e: if FPGATYPE = "s3e" generate
+               data_ram : ram_xilinx
+               generic map (
+                       DATA_ADDR_WIDTH
+               )
+               port map (
+                       clk,
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       wb_reg_nxt.byte_en,
+                       dmem_we,
+                       wb_reg_nxt.data, --ram_data,
+                       data_ram_read
+               );
+       end generate;
+       -- else generate gibt es erst mit vhdl 2008 ...
+       altera: if FPGATYPE /= "s3e" generate
        data_ram : r_w_ram_be
                generic map (
                        DATA_ADDR_WIDTH
@@ -47,6 +65,7 @@ begin
                        wb_reg_nxt.data, --ram_data,
                        data_ram_read
                );
+       end generate;
 
 uart : extension_uart 
        generic map(
@@ -62,6 +81,21 @@ uart : extension_uart
                        bus_tx
                );
        
+imp : extension_imp 
+       generic map(
+               RESET_VALUE
+               )
+       port map(
+                       clk ,
+                       reset,
+                       ext_imp,
+                       ext_imp_out,
+                       im_addr,
+                       im_data,
+                       new_im_data_out
+               );
+       
+       altera_7seg: if FPGATYPE /= "s3e" generate
 sseg : extension_7seg
        generic map(
                RESET_VALUE
@@ -75,6 +109,7 @@ sseg : extension_7seg
                sseg2,
                sseg3
                );
+       end generate;
 
 interrupt : extension_interrupt
        generic map(
@@ -304,36 +339,56 @@ begin
   ext_timer.sel <='0';
   ext_gpmp.sel <='0';
   ext_int.sel <= '0';
+  ext_imp.sel <= '0';
   
   ext_uart.wr_en <= wr_en;
   ext_7seg.wr_en <= wr_en;
   ext_timer.wr_en <= wr_en;
   ext_gpmp.wr_en <= wr_en;
   ext_int.wr_en <= wr_en;  
+  ext_imp.wr_en <= wr_en;  
 
   ext_uart.byte_en <= byte_en;
   ext_7seg.byte_en <= byte_en;
   ext_timer.byte_en <= byte_en;
   ext_gpmp.byte_en <= byte_en;
   ext_int.byte_en <= byte_en;  
+  ext_imp.byte_en <= byte_en; 
 
   ext_uart.addr <= addr;
   ext_7seg.addr <= addr;
   ext_timer.addr <= addr;
   ext_gpmp.addr <= addr;
   ext_int.addr <= addr;
+  ext_imp.addr <= addr;
 
   ext_uart.data <= data;
   ext_7seg.data <= data;
   ext_timer.data <= data;
   ext_gpmp.data <= data;
   ext_int.data <= data;
+  ext_imp.data <= data;
 
    -- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
  case addrid is
     when EXT_UART_ADDR => 
        ext_uart.sel <= enable;
-               ext_anysel <= enable;
+       ext_anysel <= enable;
+
+--             ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
+--             ext_uart.data <= ram_data;
+--             ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
+--             case wb_reg_nxt.address(1 downto 0) is
+--                             when "00" => ext_uart.byte_en <= "0001";
+--                             when "01" => ext_uart.byte_en <= "0010";
+--                             when "10" => ext_uart.byte_en <= "0100";
+--                             --when "11" => ext_uart.byte_en <= "1000";
+--                             when "11" => ext_uart.byte_en <= "1111";
+--                             when others => null;
+--                     end case;
+    when EXT_IMP_ADDR => 
+       ext_imp.sel <= enable;
+       ext_anysel <= enable;
 
 --             ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
 --             ext_uart.data <= ram_data;
@@ -349,7 +404,7 @@ begin
 
     when EXT_INT_ADDR => 
        ext_int.sel <= enable;
-               ext_anysel <= enable;
+       ext_anysel <= enable;
 
 --             ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
 --             ext_uart.data <= ram_data;