timer: added as extension modul

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index fd26a297b8e5727e9f5c2d975c600cb9b35115fd..83084c814fd385f8bdc1e32b2c9fda2ba67f921d 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -10,6 +10,7 @@ use work.extension_pkg.all;
 use work.extension_uart_pkg.all;
 use work.extension_7seg_pkg.all;
 use work.extension_imp_pkg.all;
+use work.extension_timer_pkg.all;
 
 architecture behav of writeback_stage is
 
@@ -30,8 +31,6 @@ signal sel_nxt, dmem_we, ext_anysel : std_logic;
 signal calc_mem_res : gp_register_t;
 
 begin
-
-       ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
        ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
 
        spartan3e: if FPGATYPE = "s3e" generate
@@ -42,6 +41,7 @@ begin
                port map (
                        clk,
                        data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
                        wb_reg_nxt.byte_en,
                        dmem_we,
                        wb_reg_nxt.data, --ram_data,
@@ -68,7 +68,8 @@ begin
 
 uart : extension_uart 
        generic map(
-               RESET_VALUE
+               RESET_VALUE,
+               CLK_BAUD
                )
        port map(
                        clk ,
@@ -125,6 +126,10 @@ interrupt : extension_interrupt
                int_req
 
                );
+
+timer : extension_timer
+       generic map(RESET_VALUE)
+       port map(clk, reset, ext_timer, ext_timer_out);
        
 syn: process(clk, reset)