timer: added as extension modul

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 7b57d4565c89592569fb72f709353497718d054d..83084c814fd385f8bdc1e32b2c9fda2ba67f921d 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -10,6 +10,7 @@ use work.extension_pkg.all;
 use work.extension_uart_pkg.all;
 use work.extension_7seg_pkg.all;
 use work.extension_imp_pkg.all;
+use work.extension_timer_pkg.all;
 
 architecture behav of writeback_stage is
 
@@ -30,10 +31,25 @@ signal sel_nxt, dmem_we, ext_anysel : std_logic;
 signal calc_mem_res : gp_register_t;
 
 begin
-
-       ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
        ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
 
+       spartan3e: if FPGATYPE = "s3e" generate
+               data_ram : ram_xilinx
+               generic map (
+                       DATA_ADDR_WIDTH
+               )
+               port map (
+                       clk,
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       wb_reg_nxt.byte_en,
+                       dmem_we,
+                       wb_reg_nxt.data, --ram_data,
+                       data_ram_read
+               );
+       end generate;
+       -- else generate gibt es erst mit vhdl 2008 ...
+       altera: if FPGATYPE /= "s3e" generate
        data_ram : r_w_ram_be
                generic map (
                        DATA_ADDR_WIDTH
@@ -48,10 +64,12 @@ begin
                        wb_reg_nxt.data, --ram_data,
                        data_ram_read
                );
+       end generate;
 
 uart : extension_uart 
        generic map(
-               RESET_VALUE
+               RESET_VALUE,
+               CLK_BAUD
                )
        port map(
                        clk ,
@@ -77,6 +95,7 @@ imp : extension_imp
                        new_im_data_out
                );
        
+       altera_7seg: if FPGATYPE /= "s3e" generate
 sseg : extension_7seg
        generic map(
                RESET_VALUE
@@ -90,6 +109,7 @@ sseg : extension_7seg
                sseg2,
                sseg3
                );
+       end generate;
 
 interrupt : extension_interrupt
        generic map(
@@ -106,6 +126,10 @@ interrupt : extension_interrupt
                int_req
 
                );
+
+timer : extension_timer
+       generic map(RESET_VALUE)
+       port map(clk, reset, ext_timer, ext_timer_out);
        
 syn: process(clk, reset)