removed 7seg from DT

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 7b57d4565c89592569fb72f709353497718d054d..569f2c68ed2e280c0367745ce07ab06ee2aa8d38 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -10,6 +10,7 @@ use work.extension_pkg.all;
 use work.extension_uart_pkg.all;
 use work.extension_7seg_pkg.all;
 use work.extension_imp_pkg.all;
+use work.extension_timer_pkg.all;
 
 architecture behav of writeback_stage is
 
@@ -30,10 +31,25 @@ signal sel_nxt, dmem_we, ext_anysel : std_logic;
 signal calc_mem_res : gp_register_t;
 
 begin
-
-       ext_timer_out <= (others => '0'); --TODO: delete when timer is connected
        ext_gpmp_out <= (others => '0'); --TODO: delete when gpm is connected
 
+       spartan3e: if FPGATYPE = "s3e" generate
+               data_ram : ram_xilinx
+               generic map (
+                       DATA_ADDR_WIDTH
+               )
+               port map (
+                       clk,
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       data_addr(DATA_ADDR_WIDTH+1 downto 2),
+                       wb_reg_nxt.byte_en,
+                       dmem_we,
+                       wb_reg_nxt.data, --ram_data,
+                       data_ram_read
+               );
+       end generate;
+       -- else generate gibt es erst mit vhdl 2008 ...
+       altera: if FPGATYPE /= "s3e" generate
        data_ram : r_w_ram_be
                generic map (
                        DATA_ADDR_WIDTH
@@ -48,10 +64,12 @@ begin
                        wb_reg_nxt.data, --ram_data,
                        data_ram_read
                );
+       end generate;
 
 uart : extension_uart 
        generic map(
-               RESET_VALUE
+               RESET_VALUE,
+               CLK_BAUD
                )
        port map(
                        clk ,
@@ -77,6 +95,9 @@ imp : extension_imp
                        new_im_data_out
                );
        
+       rem7seg: if "a" /= "a" generate
+
+       altera_7seg: if FPGATYPE /= "s3e" generate
 sseg : extension_7seg
        generic map(
                RESET_VALUE
@@ -84,12 +105,15 @@ sseg : extension_7seg
        port map(
                clk,
                reset,
-               ext_7seg,
-               sseg0,
-               sseg1,
-               sseg2,
-               sseg3
+               --ext_7seg,
+               ext_7seg
+               --sseg0,
+               --sseg1,
+               --sseg2,
+               --sseg3
                );
+       end generate;
+       end generate;
 
 interrupt : extension_interrupt
        generic map(
@@ -106,6 +130,10 @@ interrupt : extension_interrupt
                int_req
 
                );
+
+timer : extension_timer
+       generic map(RESET_VALUE)
+       port map(clk, reset, ext_timer, ext_timer_out);
        
 syn: process(clk, reset)
 
@@ -210,7 +238,7 @@ begin
        if (alu_jmp = '1' and wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0' and write_en = '0') then
                jump_addr <= data_ram_read;
        else
-               jump_addr <= result;    
+               jump_addr <= result;
        end if;
 
 --     if alu_jmp = '0' and br_pred = '1' and write_en = '0' then
@@ -245,7 +273,7 @@ begin
        data_addr <= (others => '0');
        dmem_we <= '0';
        
-       if (wb_reg.address(DATA_ADDR_WIDTH+2) /= '1') then
+       if (wb_reg.address(DATA_ADDR_WIDTH+3) /= '1') then
                data_out := data_ram_read;
        else
                reg_we_v := reg_we_v and ext_anysel;
@@ -282,7 +310,7 @@ begin
        
        data_out := to_stdlogicvector(to_bitvector(data_out) srl to_integer(unsigned(wb_reg.address(BYTEADDR-1 downto 0)))*byte_t'length); 
        
-       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+2) /= '1') then
+       if (wb_reg_nxt.address(DATA_ADDR_WIDTH+3) /= '1') then
                data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
                dmem_we <= wb_reg_nxt.dmem_write_en;
        end if;
@@ -429,9 +457,9 @@ begin
                                -- when "11" => ext_timer.byte_en <= "1000";
                                -- when others => null;
                        -- end case;
-       when EXT_GPMP_ADDR => 
-               ext_gpmp.sel <= enable;
-               ext_anysel <= enable;
+--     when EXT_GPMP_ADDR => 
+ --            ext_gpmp.sel <= enable;
+--             ext_anysel <= enable;
                -- ext_gpmp.wr_en <= wb_reg_nxt.dmem_write_en;
                -- ext_gpmp.data <= ram_data;
                -- ext_gpmp.addr <= wb_reg_nxt.address(wb_reg_nxt.address'high downto BYTEADDR);