removed 7seg from DT

[calu.git] / cpu / src / writeback_stage_b.vhd

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index 6a3a4e6c0e11ef5b500e29f9ba24e5ed698d9c40..569f2c68ed2e280c0367745ce07ab06ee2aa8d38 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -95,6 +95,8 @@ imp : extension_imp
                        new_im_data_out
                );
        
                        new_im_data_out
                );
        

+       rem7seg: if "a" /= "a" generate
+

        altera_7seg: if FPGATYPE /= "s3e" generate
 sseg : extension_7seg
        generic map(
        altera_7seg: if FPGATYPE /= "s3e" generate
 sseg : extension_7seg
        generic map(


@@ -103,13 +105,15 @@ sseg : extension_7seg
        port map(
                clk,
                reset,
        port map(
                clk,
                reset,

-               ext_7seg,
-               sseg0,
-               sseg1,
-               sseg2,
-               sseg3
+               --ext_7seg,
+               ext_7seg
+               --sseg0,
+               --sseg1,
+               --sseg2,
+               --sseg3

                );
        end generate;
                );
        end generate;

+       end generate;

 
 interrupt : extension_interrupt
        generic map(
 
 interrupt : extension_interrupt
        generic map(