removed 7seg from DT

[calu.git] / cpu / src / writeback_stage.vhd

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 4c1364c3e597bacccd3e3d945ea2d9442dd9f43c..ff31450b4cf8b72ee491fa393e2509c44b4c9bc5 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -10,8 +10,9 @@ entity writeback_stage is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic
-                       
+                       LOGIC_ACT : std_logic;
+                       FPGATYPE : string;
+                       CLK_BAUD : integer
                        );
        port(
                --System inputs
@@ -36,7 +37,20 @@ entity writeback_stage is
                        jump_addr : out instruction_addr_t;
                        jump : out std_logic;
                        -- hallo stefan mir adden da jetzt mal schnell an uart port :D
-                       bus_tx : out std_logic
+                       bus_tx : out std_logic;
+                       bus_rx : in std_logic;
+                       -- instruction memory program port :D
+                       new_im_data_out : out std_logic;
+                       im_addr : out gp_register_t;
+                       im_data : out gp_register_t;
+                       
+                       --sseg0 : out std_logic_vector(0 to 6);
+                       --sseg1 : out std_logic_vector(0 to 6);
+                       --sseg2 : out std_logic_vector(0 to 6);
+                       --sseg3 : out std_logic_vector(0 to 6);
+
+                       int_req : out interrupt_t
+
                );
                
 end writeback_stage;