-- active reset value
RESET_VALUE : std_logic;
-- active logic value
- LOGIC_ACT : std_logic
-
+ LOGIC_ACT : std_logic;
+ FPGATYPE : string;
+ CLK_BAUD : integer
);
port(
--System inputs
ram_data : in word_t; --ureg
alu_jmp : in std_logic; --reg
br_pred : in std_logic; --reg
- write_en : in std_logic; --reg (register file)
+ write_en : in std_logic; --reg (register file) bei jump 1 wenn addr in result
dmem_en : in std_logic; --ureg (jump addr in mem or in address)
dmem_write_en : in std_logic; --ureg
hword : in std_logic; --ureg
reg_we : out std_logic;
reg_addr : out gp_addr_t;
jump_addr : out instruction_addr_t;
- jump : out std_logic
+ jump : out std_logic;
+ -- hallo stefan mir adden da jetzt mal schnell an uart port :D
+ bus_tx : out std_logic;
+ bus_rx : in std_logic;
+ -- instruction memory program port :D
+ new_im_data_out : out std_logic;
+ im_addr : out gp_register_t;
+ im_data : out gp_register_t;
+
+ --sseg0 : out std_logic_vector(0 to 6);
+ --sseg1 : out std_logic_vector(0 to 6);
+ --sseg2 : out std_logic_vector(0 to 6);
+ --sseg3 : out std_logic_vector(0 to 6);
+
+ int_req : out interrupt_t
+
);
end writeback_stage;