default baudrate setting now in top level entity

[calu.git] / cpu / src / writeback_stage.vhd

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 9ec598638530aa97708967dca32b9ac78210de10..ea82a1edc3e045cd22365abe7181a757bdab8069 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -11,7 +11,8 @@ entity writeback_stage is
                        RESET_VALUE : std_logic;
                        -- active logic value
                        LOGIC_ACT : std_logic;
-                       FPGATYPE : string
+                       FPGATYPE : string;
+                       CLK_BAUD : integer
                        );
        port(
                --System inputs