default baudrate setting now in top level entity

diff --git a/cpu/src/core_pkg.vhd b/cpu/src/core_pkg.vhd
index 87cfcc6d6d9877899f1d76acaa34601931e66145..9731f37592de2f49322534d87c8968b0f6da25a3 100644 (file)
--- a/cpu/src/core_pkg.vhd
+++ b/cpu/src/core_pkg.vhd
@@ -127,7 +127,8 @@ package core_pkg is
                        RESET_VALUE : std_logic;
                        -- active logic value
                        LOGIC_ACT : std_logic;
-                       FPGATYPE : string
+                       FPGATYPE : string;
+                       CLK_BAUD : integer
                        );
        port(
                --System inputs

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index 452db698062de0f4f2f9cc79f30a50d2b0d4988e..6815be1dbffc6d808f0839d9c8a500f0fafcb282 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -156,7 +156,7 @@ begin
 --
 
                        writeback_st : writeback_stage
-                generic map('0', '1', "altera")
+                generic map('0', '1', "altera", 2083)
                 port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,

diff --git a/cpu/src/core_top_c2de1.vhd b/cpu/src/core_top_c2de1.vhd
index adecfeea85896300d6ace14f9f8fde867ca6ce60..0d149c1a1a97c67c2c913554fec9ec356cc3231b 100644 (file)
--- a/cpu/src/core_top_c2de1.vhd
+++ b/cpu/src/core_top_c2de1.vhd
@@ -138,7 +138,7 @@ begin
 
                                                                         
           writeback_st : writeback_stage
-                generic map(RESET_VALUE, '1', "altera")
+                generic map(RESET_VALUE, '1', "altera", 434)
                 port map(sys_clk, sys_res_n and soft_res_n, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
                 wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx, 

diff --git a/cpu/src/extension_uart.vhd b/cpu/src/extension_uart.vhd
index f5931646ca09555a8dba1bd8a4d3f90efd1df54d..07d6bda2654efe5d679d3231c149e907dcea61c1 100644 (file)
--- a/cpu/src/extension_uart.vhd
+++ b/cpu/src/extension_uart.vhd
@@ -11,7 +11,8 @@ entity extension_uart is
 
        generic (
                        -- active reset value
-                       RESET_VALUE : std_logic
+                       RESET_VALUE : std_logic;
+                       CLK_PER_BAUD : integer
                        );
        port(
                --System inputs

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index 6f6580b7db8d9df6e526523c81e04e9c1a2e3587..1bbe2b892096fd4404a5bafa13dec520f989e659 100644 (file)
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -22,7 +22,7 @@ subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
 --constant CLK_FREQ_MHZ : real := 33.33;
 --constant BAUD_RATE : integer := 115200;
 --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
- constant CLK_PER_BAUD : integer := 434;
+-- constant CLK_PER_BAUD : integer := 434;
 -- constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
 -- constant CLK_PER_BAUD : integer := 50; -- @modelsim
 
@@ -30,7 +30,8 @@ subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
         --some modules won't need all inputs/outputs
        generic (
                        -- active reset value
-                       RESET_VALUE : std_logic
+                       RESET_VALUE : std_logic;
+                       CLK_PER_BAUD : integer
                        );
        port(
                --System inputs

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 9ec598638530aa97708967dca32b9ac78210de10..ea82a1edc3e045cd22365abe7181a757bdab8069 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -11,7 +11,8 @@ entity writeback_stage is
                        RESET_VALUE : std_logic;
                        -- active logic value
                        LOGIC_ACT : std_logic;
-                       FPGATYPE : string
+                       FPGATYPE : string;
+                       CLK_BAUD : integer
                        );
        port(
                --System inputs

diff --git a/cpu/src/writeback_stage_b.vhd b/cpu/src/writeback_stage_b.vhd
index a031207123e2836ec47551455ac1df7391623ae4..78a17a451984710d71b39cd511b66c135d9e9903 100755 (executable)
--- a/cpu/src/writeback_stage_b.vhd
+++ b/cpu/src/writeback_stage_b.vhd
@@ -69,7 +69,8 @@ begin
 
 uart : extension_uart 
        generic map(
-               RESET_VALUE
+               RESET_VALUE,
+               CLK_BAUD
                )
        port map(
                        clk ,