uart und extension anbindung

[calu.git] / cpu / src / writeback_stage.vhd

diff --git a/cpu/src/writeback_stage.vhd b/cpu/src/writeback_stage.vhd
index 73c5df43499e1401bc04a496f9cc5b941d0cab4a..956ba51312add5b47655ea9aca1f00d10d3222cd 100644 (file)
--- a/cpu/src/writeback_stage.vhd
+++ b/cpu/src/writeback_stage.vhd
@@ -37,6 +37,7 @@ entity writeback_stage is
                        jump : out std_logic;
                        -- hallo stefan mir adden da jetzt mal schnell an uart port :D
                        bus_tx : out std_logic;
+                       bus_rx : in std_logic;
                        
                        sseg0 : out std_logic_vector(0 to 6);
                        sseg1 : out std_logic_vector(0 to 6);