uart und extension anbindung
[calu.git] / cpu / src / rs232_rx_arc.vhd
index 1bdc472806753a562cbf6c9c933d4f3969bcb9dc..924a3ce9a6be8bc8aba7bed482f87ccfb622d05b 100755 (executable)
@@ -26,6 +26,8 @@ architecture beh of rs232_rx is
        signal cnt, cnt_next : integer := 0;
        signal baud_cnt, baud_cnt_next : std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
        signal rx_data_int, rx_data_nxt, rx_data_res_int, rx_data_res_nxt : uart_data;
+       signal sync : std_logic_vector(1 to SYNC_STAGES);
+       signal bus_rx : std_logic;
        
 begin
        -- syncronisierungs Prozess
@@ -37,6 +39,7 @@ begin
                        cnt <= 0;
                        rx_data_res_int <= x"00";
                        baud_cnt <= (others => '0');
+                       sync <= (others => '1');
 
                elsif rising_edge(sys_clk) then
                        -- sync Zustand, uebernehmen der next-Signale
@@ -48,11 +51,17 @@ begin
                        rx_data_res_int <= rx_data_res_nxt;
                        new_rx_data <= new_rx_data_nxt;
 
+                       sync(1) <= bus_rx_unsync;
+                       for i in 2 to SYNC_STAGES loop
+                               sync(i) <= sync(i - 1);
+                       end loop;
+                       
                end if;
        end process;
 
        -- setzen des Ausgangsignals, Rxt-Daten
        rx_data <= rx_data_res_int;
+       bus_rx <= sync(SYNC_STAGES);
 
        -- Zustandsmaschienen Prozess
        rs232_states : process(sys_clk,state,cnt, bus_rx, bus_rx_last, baud_cnt,bus_rx_int,bd_rate)