ldi add finished

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index 4f1a0e0e8d8080bf4ea0e40e91ca9e46c06873fb..6db0659bae58fa5baa8f7ac2a2f20d9db6ddf7ac 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -12,9 +12,9 @@ architecture behaviour of r_w_ram is
        
                                                                        -- r0 = 0, r1 = 1, r2 = 3, r3 = A
 
-       signal ram : RAM_TYPE := (  0 => "11100001000010001000000000111000", -- r1 = 7
-                                   1 => "11100001000100010000000000101000", -- r2 = 5
-                                   2 => "11100001000110011000000000100000", -- r3 = 4
+       signal ram : RAM_TYPE := (  0 => "11101101000010000000000000111000", -- r1 = 7
+                                   1 => "11101101000100000000000000101000", -- r2 = 5
+                                   2 => "11101101000110000000000000100000", -- r3 = 4
                                    3 => "11100000001000010001100000000000", -- r4 = r2 + r3
                                    4 => "11100010001010100000100000000000", -- r5 = r4 and r1
                                  others => x"F0000000");