-- r0 = 0, r1 = 1, r2 = 3, r3 = A
signal ram : RAM_TYPE := (
-
-
- 0 => "11101101000000000000000001011000", -- r0 = 11
- 1 => "11101101000010000000000000111000", -- r1 = 7
- 2 => "11100111100010000000000000000000", --stw
- 3 => "11101101000000000000000000011000", -- r0 = 3
- 4 => "11101101000010000000000001001000", -- r1 = 9
- 5 => "11100111000010000000000000000000", --ldw
- 6 => "11101101000000000000000000011000", -- r0 = 3
- 7 => "11101101000010000000000001001000", -- r1 = 9
--8 => "11100111100010000000000000000000", --stw
-- 0 => "11101101000000000000000000000000", --ldi
-- 1 => "11101101001000000000000000000000", --ldi
process(clk)
begin
if rising_edge(clk) then
- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+ -- data_out <= ram(to_integer(UNSIGNED(rd_addr)));
+ case rd_addr is
+ when "00000000000" => data_out <= x"ed2802d0"; -- ldi r5, 0x5a;;
+ when "00000000100" => data_out <= x"ed008058"; -- ldi r0, 0x100b;;
+ when "00000001000" => data_out <= x"e7a80000"; -- stw r5, 0(r0);;
+ when others => data_out <= x"07a80000";
+ end case;
if wr_en = '1' then
ram(to_integer(UNSIGNED(wr_addr))) <= data_in;