subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
- signal ram : RAM_TYPE := (--0 => "11100000000000011001000000000000", -- r0 = r3 + r2 (always)
- -- 1 => "11100101000000001000100000000000", -- r0 = r1 << 0 (always)
- -- 2 => "11100000000010000001100000000000", -- r1 = r0 + r3 (always)
- -- 3 => "11100000101000000001000000000000",
- -- 4 => "11100001000110010111011001101100",
- 0 => "11101100000000001000000000000000", -- cmp r0 , r1
- 1 => "00000000000100000000100000000000",
- 2 => "00000000001110000001000000000000",
- 3 => "11100001000110010000011001101100",
+ signal ram : RAM_TYPE := ( 0 => "11100000000100001000000000000000", --add r2, r1, r0
+ 1 => "11100000000110001000000000000000", --add r3, r1, r0
+ 2 => "11100000001000011001000000000000", --add r4, r3, r2
+ 3 => "11100000000100001000000000000000", --add r2, r1, r0
+ 4 => "11100000000110001000000000000000", --add r3, r1, r0
+ 5 => "11100000001000011001000000000000", --add r4, r3, r2
+ 6 => "11101100000000001000000000000000", --cmp r0 , r1
+ 7 => "00000000001010101010000000000001", --addnqd r5, r5, r4
+ 8 => "00000000001010101010000000000000", --addnq r5, r5, r4
+ 9 => "11101100001000100000000000000000", --cmp r4 , r4
+ 10 => "00000001001100001000000001010000", --addinq r5, r1, 10
+ 11 => "00010001001100001000000001010000", --addieq r5, r1, 10
+ 12 => "00010001101100110000000001010000", --subieq r5, r5, 10
+ 13 => "11100000000100001000000000000000", --add r2, r1, r0
+ 14 => "11100010000100001000000000000000", --and r2, r1, r0
+ 15 => "11101100000000001000000000000000", --cmp r0 , r1
+ 16 => "10000000001010101010000000000001", --addabd r5, r5, r4
+ 17 => "10110011101110001000010000110001", --orxltd r7, 1086
+ 18 => "10110101001110001000010000000001", --shiftltd r7, r1, 1
+ 19 => "01010101001110001000100000000001", --shiftltd r7, r1, 2
others => x"F0000000");
+
begin
process(clk)
begin