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forward unit testcases (from assignments), everything works fine!
[calu.git]
/
cpu
/
src
/
r2_w_ram_b.vhd
diff --git
a/cpu/src/r2_w_ram_b.vhd
b/cpu/src/r2_w_ram_b.vhd
index c20c8b14ef5ed12e87e6f2b625f993b8ec3e3996..64c8da4e21f0ca689be0f3853d5acddfbcc893b3 100644
(file)
--- a/
cpu/src/r2_w_ram_b.vhd
+++ b/
cpu/src/r2_w_ram_b.vhd
@@
-12,9
+12,9
@@
architecture behaviour of r2_w_ram is
signal ram : RAM_TYPE := (
0 => x"00000000",
- 1 => x"0000000
1
",
- 2 => x"0000000
A
",
- 3 => x"0000000
3
",
+ 1 => x"0000000
0
",
+ 2 => x"0000000
0
",
+ 3 => x"0000000
0
",
others=> (others => '0'));
begin