gitignore für sim

[calu.git] / cpu / src / r2_w_ram_b.vhd

diff --git a/cpu/src/r2_w_ram_b.vhd b/cpu/src/r2_w_ram_b.vhd
index 84a3a94b150f6747a4319645f7c37f86e01810c3..3c71ade0c41a6d254832c95865d877cf64f11b35 100644 (file)
--- a/cpu/src/r2_w_ram_b.vhd
+++ b/cpu/src/r2_w_ram_b.vhd
@@ -10,7 +10,12 @@ architecture behaviour of r2_w_ram is
        subtype RAM_ENTRY_TYPE is std_logic_vector(DATA_WIDTH -1 downto 0);
        type RAM_TYPE is array (0 to (2**ADDR_WIDTH)-1) of RAM_ENTRY_TYPE;
        
-       signal ram : RAM_TYPE := (others=> x"00000001");
+       signal ram : RAM_TYPE := (
+                               0 => x"00000010",
+                               1 => x"00110010",
+                               2 => x"000000FF",
+                               3 => x"00AB00BA",
+                               others=> x"00000000");
 
 begin
        process(clk)