use work.common_pkg.all;
use work.core_pkg.all;
-
+use work.extension_pkg.all;
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture behavior of pipeline_tb is
- constant cc : time := 30 ns; -- test clock period
-
+ constant cc : time := 20 ns; -- test clock period
+ constant SYS_CLOCK_FREQ : integer := 50000000;
+ constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200;
+
signal sys_clk_pin : std_logic;
signal sys_res_n_pin : std_logic;
--Data input
signal branch_prediction_bit_pin : std_logic;
signal alu_jump_bit_pin : std_logic;
signal instruction_pin : instruction_word_t;
+ signal prog_cnt : instruction_addr_t;
signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
signal reg_wr_data_pin : gp_register_t;
signal reg_we_pin : std_logic;
- signal reg1_rd_data_pin : gp_register_t;
- signal reg2_rd_data_pin : gp_register_t;
-
+ signal to_next_stage_pin : dec_op;
+
+ signal result_pin : gp_register_t;--reg
+ signal result_addr_pin : gp_addr_t;--reg
+ signal addr_pin : word_t; --memaddr
+ signal data_pin : gp_register_t; --mem data --ureg
+ signal alu_jump_pin : std_logic;--reg
+ signal brpr_pin : std_logic; --reg
+ signal wr_en_pin : std_logic;--regop --reg
+ signal dmem_pin : std_logic;--memop
+ signal dmem_wr_en_pin : std_logic;
+ signal hword_pin : std_logic;
+ signal byte_s_pin, tx_pin, rx_pin : std_logic;
+
+ signal gpm_in_pin : extmod_rec;
+ signal gpm_out_pin : gp_register_t;
+ signal nop_pin : std_logic;
+
+ signal cycle_cnt : integer;
+
+ signal sseg0, sseg1, sseg2, sseg3 : std_logic_vector(0 to 6);
+ signal int_req_pin : interrupt_t;
+
+ signal new_im_data :std_logic;
+ signal im_addr, im_data : gp_register_t;
begin
--System inputs
clk => sys_clk_pin, --: in std_logic;
reset => sys_res_n_pin, --: in std_logic;
-
+ s_reset => '0',
--Data inputs
jump_result => jump_result_pin, --: in instruction_addr_t;
prediction_result => prediction_result_pin, --: in instruction_addr_t;
branch_prediction_bit => branch_prediction_bit_pin, --: in std_logic;
alu_jump_bit => alu_jump_bit_pin, --: in std_logic;
+ new_im_data_in => new_im_data,
+ im_addr => im_addr,
+ im_data => im_data,
--Data outputs
- instruction => instruction_pin --: out instruction_word_t
- );
+ instruction => instruction_pin, --: out instruction_word_t
+ prog_cnt => prog_cnt,
+ int_req => int_req_pin
+ );
decode_st : decode_stage
generic map (
--Data inputs
instruction => instruction_pin, --: in instruction_word_t;
+ prog_cnt => prog_cnt,
reg_w_addr => reg_w_addr_pin, --: in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
reg_wr_data => reg_wr_data_pin, --: in gp_register_t;
reg_we => reg_we_pin, --: in std_logic;
+ nop => nop_pin,
--Data outputs
- reg1_rd_data => reg1_rd_data_pin, --: gp_register_t;
- reg2_rd_data => reg2_rd_data_pin, --: gp_register_t;
branch_prediction_res => prediction_result_pin, --: instruction_word_t;
- branch_prediction_bit => branch_prediction_bit_pin --: std_logic
+ branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
+ to_next_stage => to_next_stage_pin
);
+ exec_st : execute_stage
+ generic map('0')
+ port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin,reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+ data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
+
+ writeback_st : writeback_stage
+ generic map('0', '1', "altera",50)
+ port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
+ wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req_pin);
+
+ nop_pin <= (alu_jump_bit_pin);-- xor brpr_pin);
+
-------------------------------------------------------------------------------
-- generate simulation clock
-------------------------------------------------------------------------------
wait for cc/2;
end process CLKGEN;
+
+ cnt : process(sys_clk_pin, sys_res_n_pin)
+
+ begin
+
+ if (sys_res_n_pin = '0') then
+ cycle_cnt <= 0;
+ elsif (sys_clk_pin'event and sys_clk_pin = '1') then
+ cycle_cnt <= cycle_cnt + 1;
+ end if;
+
+ end process cnt;
-------------------------------------------------------------------------------
-- test the design
-------------------------------------------------------------------------------
wait until sys_clk_pin = '1' and sys_clk_pin'event;
end loop;
end;
+
+ procedure txd(trans_data : in std_logic_vector) is
+ begin
+ for i in 0 to 9 loop
+ rx_pin <= trans_data(i);
+ report "bit: " & std_logic'image(trans_data(i));
+ dummy <= not dummy;
+ wait on dummy;
+ -- icwait(BAUD_COUNT);
+ icwait(50);
+ end loop;
+ end txd;
+
begin
-----------------------------------------------------------------------------
-- initial reset
-----------------------------------------------------------------------------
sys_res_n_pin <= '0';
- reg_w_addr_pin <= (others => '0');
- reg_wr_data_pin <= (others => '0');
- reg_we_pin <= '0';
+ rx_pin <= '1';
+-- reg_w_addr_pin <= (others => '0');
+-- reg_wr_data_pin <= (others => '0');
+-- reg_we_pin <= '0';
icwait(10);
dummy <= '1';
sys_res_n_pin <= '1';
wait until sys_res_n_pin = '1';
+ icwait(10);
+
+ txd("0000100101");
+ icwait(600);
+ icwait(600);
- icwait(100000);
+ txd("0000100101");
+ icwait(600000000);
---------------------------------------------------------------------------
-- exit testbench
end for;
for decode_st : decode_stage use entity work.decode_stage(behav);
end for;
+ for exec_st : execute_stage use entity work.execute_stage(behav);
+ end for;
+ for writeback_st : writeback_stage use entity work.writeback_stage(behav);
+ end for;
end for;
end pipeline_conf_beh;
projects / calu.git / blobdiff