added pipe 2 reg, testbench, top_level_entity, ...

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index 43c0c9870e000ab33017c0101a2e2c13ab3094ec..e856e69ec98343498a5a36bc4c5846c24a22a541 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -35,9 +35,7 @@ architecture behavior of pipeline_tb is
                signal reg_w_addr_pin : std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
                signal reg_wr_data_pin : gp_register_t;
                signal reg_we_pin : std_logic;
-               signal reg1_rd_data_pin : gp_register_t;
-               signal reg2_rd_data_pin : gp_register_t;
-
+               signal to_next_stage_pin : dec_op;
 
 begin
 
@@ -98,10 +96,9 @@ begin
                        reg_we => reg_we_pin, --: in std_logic;
 
                --Data outputs
-                       reg1_rd_data => reg1_rd_data_pin, --: gp_register_t;
-                       reg2_rd_data => reg2_rd_data_pin, --: gp_register_t;
                        branch_prediction_res => prediction_result_pin, --: instruction_word_t;
-                       branch_prediction_bit => branch_prediction_bit_pin --: std_logic
+                       branch_prediction_bit => branch_prediction_bit_pin, --: std_logic
+                       to_next_stage => to_next_stage_pin
                        
                );