-------------------------------------------------------------------------------
architecture behavior of pipeline_tb is
- constant cc : time := 30 ns; -- test clock period
-
+ constant cc : time := 20 ns; -- test clock period
+ constant SYS_CLOCK_FREQ : integer := 50000000;
+ constant BAUD_COUNT : integer := SYS_CLOCK_FREQ/115200;
+
signal sys_clk_pin : std_logic;
signal sys_res_n_pin : std_logic;
--Data input
signal dmem_pin : std_logic;--memop
signal dmem_wr_en_pin : std_logic;
signal hword_pin : std_logic;
- signal byte_s_pin, tx_pin : std_logic;
+ signal byte_s_pin, tx_pin, rx_pin : std_logic;
signal gpm_in_pin : extmod_rec;
signal gpm_out_pin : gp_register_t;
generic map('0', '1')
port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, sseg0, sseg1, sseg2, sseg3);
+ reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin, tx_pin, rx_pin, sseg0, sseg1, sseg2, sseg3);
wait until sys_clk_pin = '1' and sys_clk_pin'event;
end loop;
end;
+
+ procedure txd(trans_data : in std_logic_vector) is
+ begin
+ for i in 0 to 9 loop
+ rx_pin <= trans_data(i);
+ dummy <= not dummy;
+ wait on dummy;
+ icwait(BAUD_COUNT);
+ end loop;
+ end txd;
+
begin
-----------------------------------------------------------------------------
sys_res_n_pin <= '1';
wait until sys_res_n_pin = '1';
+ icwait(10);
+
+ txd("0100000101");
icwait(1000000000);