uart: bugfix fuer busy reset

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index e1135d411ac9ed4cfda5a391d7f9c6de13213815..da886861d1cb98700e2b24352ef25f918ee7fca7 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -193,7 +193,8 @@ begin
                        rx_pin <= trans_data(i);
                        dummy <= not dummy;
                        wait on dummy;
-                       icwait(BAUD_COUNT);
+                       -- icwait(BAUD_COUNT);
+                       icwait(15);
                end loop;
        end txd;