Fixed some bugs.

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index e856e69ec98343498a5a36bc4c5846c24a22a541..c1c6b0c79f978416379359ce24f45f9a995a5f47 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -4,7 +4,6 @@ use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.core_pkg.all;
-
 -------------------------------------------------------------------------------
 -- ENTITY
 -------------------------------------------------------------------------------
@@ -37,6 +36,18 @@ architecture behavior of pipeline_tb is
                signal reg_we_pin : std_logic;
                signal to_next_stage_pin : dec_op;
 
+                 signal result_pin : gp_register_t;--reg
+                 signal result_addr_pin : gp_addr_t;--reg
+                 signal addr_pin : word_t; --memaddr
+                 signal data_pin : gp_register_t; --mem data --ureg
+                 signal alu_jump_pin : std_logic;--reg
+                 signal brpr_pin  : std_logic;  --reg
+                 signal wr_en_pin : std_logic;--regop --reg
+                 signal dmem_pin  : std_logic;--memop
+                 signal dmem_wr_en_pin : std_logic;
+                 signal hword_pin  : std_logic;
+                 signal byte_s_pin : std_logic;
+
 begin
 
 --             instruction_ram : r_w_ram
@@ -101,6 +112,16 @@ begin
                        to_next_stage => to_next_stage_pin
                        
                );
+          exec_st : execute_stage
+                generic map('0')
+                port map(sys_clk_pin, sys_res_n_pin,to_next_stage_pin, result_pin, result_addr_pin,addr_pin,
+                data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin);
+
+          writeback_st : writeback_stage
+                generic map('0', '1')
+                port map(sys_clk_pin, sys_res_n_pin, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
+                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin);
 
 
 
@@ -133,9 +154,9 @@ begin
     -- initial reset
     -----------------------------------------------------------------------------
        sys_res_n_pin <= '0';
-       reg_w_addr_pin <= (others => '0');
-       reg_wr_data_pin <= (others => '0');
-       reg_we_pin <= '0';
+--     reg_w_addr_pin <= (others => '0');
+--     reg_wr_data_pin <= (others => '0');
+--     reg_we_pin <= '0';
 
        icwait(10);
        dummy <= '1';
@@ -166,6 +187,10 @@ configuration pipeline_conf_beh of pipeline_tb is
     end for;
     for decode_st : decode_stage use entity work.decode_stage(behav);
     end for;
+    for exec_st : execute_stage use entity work.execute_stage(behav);
+    end for;
+    for writeback_st : writeback_stage use entity work.writeback_stage(behav);
+    end for;
 
   end for;
 end pipeline_conf_beh;