fibonacci tested rc1, 107 cycles, 1k2le, 57MHz

[calu.git] / cpu / src / pipeline_tb.vhd

diff --git a/cpu/src/pipeline_tb.vhd b/cpu/src/pipeline_tb.vhd
index fd86d721e9910f178d5ed2f58e90a803241d47d6..7392a95a350758f4750410e401947ced54d52c38 100644 (file)
--- a/cpu/src/pipeline_tb.vhd
+++ b/cpu/src/pipeline_tb.vhd
@@ -54,6 +54,8 @@ architecture behavior of pipeline_tb is
                                 signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
 
+                signal cycle_cnt : integer;
+
 
 begin
 
@@ -149,6 +151,18 @@ begin
     wait for cc/2;
   end process CLKGEN;
   
+
+  cnt : process(sys_clk_pin, sys_res_n_pin)
+
+  begin
+
+       if (sys_res_n_pin = '0') then
+               cycle_cnt <= 0;
+       elsif (sys_clk_pin'event and sys_clk_pin = '1') then
+               cycle_cnt <= cycle_cnt + 1;
+       end if;
+
+  end process cnt;
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 -- test the design
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