spartan3e: BRAM gehaxe. lesbarer und wird auch richtig(er) instanziert

[calu.git] / cpu / src / mem_pkg.vhd

diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd
index 72ecb58f66ddd896025c2f0556fe1140142b4e36..425af910287f0e10682f16532ddb9884f74f23b3 100644 (file)
--- a/cpu/src/mem_pkg.vhd
+++ b/cpu/src/mem_pkg.vhd
@@ -23,6 +23,59 @@ package mem_pkg is
                        data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
                );
        end component r_w_ram;
+
+       component r_w_ram_be is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               clk : in std_logic;
+
+               waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+               be : in std_logic_vector (3 downto 0);
+               
+               we : in std_logic;
+
+               wdata : in std_logic_vector(31 downto 0);
+               
+               q : out std_logic_vector(31 downto 0)
+       );
+       end component r_w_ram_be;
+
+       component ram_xilinx is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               clk : in std_logic;
+
+               waddr, raddr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+
+               be : in std_logic_vector (3 downto 0);
+               
+               we : in std_logic;
+
+               wdata : in std_logic_vector(31 downto 0);
+               
+               q : out std_logic_vector(31 downto 0)
+       );
+       end component ram_xilinx;
+
+       component rom is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high;
+                               DATA_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               --System inputs
+                       clk : in std_logic;
+               --Input
+                       rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);                   
+               --Output
+                       data_out : out std_logic_vector(DATA_WIDTH-1 downto 0)
+               );
+       end component rom;
        
        component r2_w_ram is
        generic (