soft reset

[calu.git] / cpu / src / fetch_stage_b.vhd

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index fb0e7fdb1bb24e235fbc4539b2c42323b524af36..f01bad8f68c4b3b9f3fc2b1700f6e56c0c7812d4 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -52,22 +52,27 @@ begin
 
        if (reset = RESET_VALUE) then
                instr_r_addr <= (others => '0');
-               rom_ram <= ROM_USE;     
+               rom_ram <= ROM_USE;
                led2 <= '0';
        elsif rising_edge(clk) then
                instr_r_addr <= instr_r_addr_nxt;               
                rom_ram <= rom_ram_nxt;
-               led2 <= rom_ram_nxt;
+               led2 <= rom_ram; --rom_ram_nxt;
        end if;
        
 end process; 
 
 
-asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
+asyn: process(reset, s_reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
 variable instr_pc  : instruction_addr_t;
 begin
        rom_ram_nxt <= rom_ram;
-
+       
+       if (s_reset = RESET_VALUE) then
+               rom_ram_nxt <= RAM_USE;
+               instr_r_addr_nxt <= (others => '0');
+       end if;
+       
        case rom_ram is
                when ROM_USE =>
                        instruction <= instr_rd_data_rom;