port(
--System input pins
sys_res : in std_logic;
+ soft_res : in std_logic;
sys_clk : in std_logic;
-- result : out gp_register_t;
-- reg_wr_data : out gp_register_t
signal nop_pin : std_logic;
signal sync : std_logic_vector(1 to SYNC_STAGES);
- signal sys_res_n : std_logic;
+ signal sync2 : std_logic_vector(1 to SYNC_STAGES);
+ signal sys_res_n, soft_res_n : std_logic;
signal int_req : interrupt_t;
--System inputs
clk => sys_clk, --: in std_logic;
reset => sys_res_n, --: in std_logic;
+ s_reset => soft_res_n,
--Data inputs
jump_result => jump_result_pin, --: in instruction_addr_t;
port map (
--System inputs
clk => sys_clk, --: in std_logic;
- reset => sys_res_n, -- : in std_logic;
+ reset => sys_res_n and soft_res_n, -- : in std_logic;
--Data inputs
instruction => instruction_pin, --: in instruction_word_t;
exec_st : execute_stage
generic map(RESET_VALUE)
- port map(sys_clk, sys_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
+ port map(sys_clk, sys_res_n and soft_res_n,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
-
--- vers_nxt.result <= result_pin;
--- vers_nxt.result_addr <= result_addr_pin;
--- vers_nxt.address <= addr_pin;
--- vers_nxt.ram_data <= data_pin;
--- vers_nxt.alu_jmp <= alu_jump_pin;
--- vers_nxt.br_pred <= brpr_pin;
--- vers_nxt.write_en <= wr_en_pin;
--- vers_nxt.dmem_en <= dmem_pin;
--- vers_nxt.dmem_write_en <= dmem_wr_en_pin;
--- vers_nxt.hword <= hword_pin;
--- vers_nxt.byte_s <= byte_s_pin;
writeback_st : writeback_stage
generic map(RESET_VALUE, '1', "altera")
- port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
+ port map(sys_clk, sys_res_n and soft_res_n, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin,
wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
new_im_data, im_addr, im_data, sseg0, sseg1, sseg2, sseg3, int_req);
--- writeback_st : writeback_stage
--- generic map(RESET_VALUE, '1', "altera")
--- port map(sys_clk, sys_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred,
--- vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
--- reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,
--- -- instruction memory program port :D
--- new_im_data, im_addr, im_data,
--- sseg0, sseg1, sseg2, sseg3, int_req);
---
syn: process(sys_clk, sys_res)
for i in 2 to SYNC_STAGES loop
sync(i) <= sync(i - 1);
end loop;
+
+ sync2(1) <= soft_res;
+ for i in 2 to SYNC_STAGES loop
+ sync2(i) <= sync2(i - 1);
+ end loop;
end if;
end process;
sys_res_n <= sync(SYNC_STAGES);
+soft_res_n <= sync2(SYNC_STAGES);
nop_pin <= (alu_jump_bit_pin); -- xor brpr_pin);
jump_result <= prog_cnt_pin; --jump_result_pin;
if (reset = RESET_VALUE) then
instr_r_addr <= (others => '0');
- rom_ram <= ROM_USE;
+ rom_ram <= ROM_USE;
led2 <= '0';
elsif rising_edge(clk) then
instr_r_addr <= instr_r_addr_nxt;
rom_ram <= rom_ram_nxt;
- led2 <= rom_ram_nxt;
+ led2 <= rom_ram; --rom_ram_nxt;
end if;
end process;
-asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
+asyn: process(reset, s_reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom, int_req)
variable instr_pc : instruction_addr_t;
begin
rom_ram_nxt <= rom_ram;
-
+
+ if (s_reset = RESET_VALUE) then
+ rom_ram_nxt <= RAM_USE;
+ instr_r_addr_nxt <= (others => '0');
+ end if;
+
case rom_ram is
when ROM_USE =>
instruction <= instr_rd_data_rom;