gitignore für sim

[calu.git] / cpu / src / fetch_stage_b.vhd

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index e774901a01dc6b93b514d15d9d6e707886ccc8fb..67dde3cc764e392975ca730a19f9f76ad68f1130 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -45,13 +45,17 @@ begin
 end process; 
 
 
-asyn: process(instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
+asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
 
 begin
 
        instruction <= instr_rd_data;
        instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
 
+       if (reset = RESET_VALUE) then
+               instr_r_addr_nxt <= (others => '0');
+       end if;
+
        if (alu_jump_bit = LOGIC_ACT) then
                instr_r_addr_nxt <= jump_result;        
        elsif (branch_prediction_bit = LOGIC_ACT) then