added instruction rom/ram switch, added new data signaling bit in uart.

[calu.git] / cpu / src / fetch_stage_b.vhd

diff --git a/cpu/src/fetch_stage_b.vhd b/cpu/src/fetch_stage_b.vhd
index e1faf1fd819cd8680904b1a097bfd217e61250e0..1ff0fad814872a115dcfba8b1fd80baa0a1bdb4d 100644 (file)
--- a/cpu/src/fetch_stage_b.vhd
+++ b/cpu/src/fetch_stage_b.vhd
@@ -13,7 +13,8 @@ signal instr_r_addr    : instruction_addr_t;
 signal instr_r_addr_nxt  : instruction_addr_t;
 signal instr_we         : std_logic;
 signal instr_wr_data    : instruction_word_t;
-signal instr_rd_data    : instruction_word_t;
+signal instr_rd_data_rom, instr_rd_data         : instruction_word_t;
+signal rom_ram, rom_ram_nxt : std_logic;
 
 begin
 
@@ -31,6 +32,19 @@ begin
                        instr_wr_data,
                        instr_rd_data
                );
+               
+       instruction_rom : rom
+               generic map (
+                       ROM_INSTR_ADDR_WIDTH,
+                       WORD_WIDTH
+               )
+               
+               port map (
+                       clk,
+                       instr_r_addr_nxt(ROM_INSTR_ADDR_WIDTH-1 downto 0),
+                       instr_rd_data_rom
+               );
+               
 
 syn: process(clk, reset)
 
@@ -38,20 +52,36 @@ begin
 
        if (reset = RESET_VALUE) then
                instr_r_addr <= (others => '0');
+               rom_ram <= ROM_USE;
        elsif rising_edge(clk) then
                instr_r_addr <= instr_r_addr_nxt;               
+               rom_ram <= rom_ram_nxt;
        end if;
        
 end process; 
 
 
-asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data)
+asyn: process(reset, instr_r_addr, jump_result, prediction_result, branch_prediction_bit, alu_jump_bit, instr_rd_data, rom_ram, instr_rd_data_rom)
 
 begin
 
-       instruction <= instr_rd_data;
+       rom_ram_nxt <= rom_ram;
+
+       case rom_ram is
+               when ROM_USE =>
+                       instruction <= instr_rd_data_rom;
+               when RAM_USE =>
+                       instruction <= instr_rd_data;
+               when others => 
+                       instruction <= x"F0000000";
+       end case;
        instr_r_addr_nxt <= std_logic_vector(unsigned(instr_r_addr) + 1);
 
+       if (instr_r_addr(ROM_INSTR_ADDR_WIDTH) = '1') then
+               rom_ram_nxt <= RAM_USE;
+               instr_r_addr_nxt <= (others => '0');
+       end if;
+       
        if (reset = RESET_VALUE) then
                instr_r_addr_nxt <= (others => '0');
        end if;