soft reset

[calu.git] / cpu / src / fetch_stage.vhd

diff --git a/cpu/src/fetch_stage.vhd b/cpu/src/fetch_stage.vhd
index c81e2ac14affda3e8addf55cbd590b220cf3a1d4..c23189ce1d3736fea9543aa98e67135eedc52f9f 100644 (file)
--- a/cpu/src/fetch_stage.vhd
+++ b/cpu/src/fetch_stage.vhd
@@ -2,7 +2,8 @@ library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
-use work.common_pkg;
+use work.common_pkg.all;
+use work.core_pkg.all;
 
 entity fetch_stage is
 
@@ -10,22 +11,31 @@ entity fetch_stage is
                        -- active reset value
                        RESET_VALUE : std_logic;
                        -- active logic value
-                       LOGIC_ACT : std_logic;
+                       LOGIC_ACT : std_logic
                        
                        );
        port(
                --System inputs
                        clk : in std_logic;
                        reset : in std_logic;
+                       s_reset : in std_logic;
                
                --Data inputs
                        jump_result : in instruction_addr_t;
                        prediction_result : in instruction_addr_t;
                        branch_prediction_bit : in std_logic;
                        alu_jump_bit : in std_logic;
+                       int_req : in interrupt_t;
+               -- instruction memory program port :D
+                       new_im_data_in : in std_logic;
+                       im_addr : in gp_register_t;
+                       im_data : in gp_register_t;
 
                --Data outputs
-                       instruction : out instruction_word_t
+                       instruction : out instruction_word_t;
+                       prog_cnt : out instruction_addr_t;
+               -- debug
+                       led2 : out std_logic
                );
                
 end fetch_stage;