lustiger modelsim fix...

[calu.git] / cpu / src / extension_uart_pkg.vhd

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index f9729920af1d30d3948afa49d48b699c300eaa9d..a7f14d9442c611e0b4820308107ec3409b31afba 100644 (file)
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -23,8 +23,8 @@ subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
 --constant BAUD_RATE : integer := 115200;
 --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
 -- constant CLK_PER_BAUD : integer := 434;
--- constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
-constant CLK_PER_BAUD : integer := 15; -- @modelsim
+constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 50; -- @modelsim
 
  component extension_uart is
         --some modules won't need all inputs/outputs