lustiger modelsim fix...

[calu.git] / cpu / src / extension_uart_pkg.vhd

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index 60f2ffa00c6626b9c32284acc367056b11e8f7fd..a7f14d9442c611e0b4820308107ec3409b31afba 100644 (file)
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -16,13 +16,15 @@ package extension_uart_pkg is
 --RS232
 constant UART_WIDTH : integer := 8;
 subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
-constant BAUD_RATE_WITH : integer := 16;
-subtype baud_rate_l is std_logic_vector(BAUD_RATE_WITH-1 downto 0);
+constant BAUD_RATE_WIDTH : integer := 16;
+subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
 --CLKs
 --constant CLK_FREQ_MHZ : real := 33.33;
 --constant BAUD_RATE : integer := 115200;
 --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
-constant CLK_PER_BAUD : integer := 434;
+-- constant CLK_PER_BAUD : integer := 434;
+constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 50; -- @modelsim
 
  component extension_uart is
         --some modules won't need all inputs/outputs
@@ -37,6 +39,8 @@ constant CLK_PER_BAUD : integer := 434;
                -- general extension interface                  
                        ext_reg  : in extmod_rec;
                        data_out : out gp_register_t;
+
+                       uart_int : out std_logic;
                -- Input
                        bus_rx : in std_logic;
                -- Ouput
@@ -70,7 +74,8 @@ end component rs232_tx;
 component rs232_rx is
        generic (
                -- active reset value
-               RESET_VALUE : std_logic
+               RESET_VALUE : std_logic;
+               SYNC_STAGES : integer range 2 to integer'high
                );
 
        port(
@@ -79,7 +84,7 @@ component rs232_rx is
                sys_res_n : in std_logic;
 
                --Bus
-               bus_rx : in std_logic;
+               bus_rx_unsync : in std_logic;
 
                --To sendlogic
                new_rx_data : out std_logic;