default baudrate setting now in top level entity

[calu.git] / cpu / src / extension_uart_pkg.vhd

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index 9a2a52f3dd4a4aac5b3a8f12c0e4235014b876d9..1bbe2b892096fd4404a5bafa13dec520f989e659 100644 (file)
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -23,13 +23,15 @@ subtype baud_rate_l is std_logic_vector(BAUD_RATE_WIDTH-1 downto 0);
 --constant BAUD_RATE : integer := 115200;
 --constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAUD_RATE) - 0.5);
 -- constant CLK_PER_BAUD : integer := 434;
-constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 2083; -- @uni, bei 20MHz und 9600 Baud
+-- constant CLK_PER_BAUD : integer := 50; -- @modelsim
 
  component extension_uart is
         --some modules won't need all inputs/outputs
        generic (
                        -- active reset value
-                       RESET_VALUE : std_logic
+                       RESET_VALUE : std_logic;
+                       CLK_PER_BAUD : integer
                        );
        port(
                --System inputs