interrupt version 1

[calu.git] / cpu / src / extension_uart_b.vhd

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 2eda02bcd7b6a8390d20386d14c472b0d4c67a82..66112759340f978bfaedab5dbe7e38e21697c0d9 100644 (file)
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -16,6 +16,8 @@ signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, t
 signal         bd_rate : baud_rate_l;
 signal rx_data : std_logic_vector(7 downto 0);
 
+signal uart_int_nxt : std_logic;
+
 signal uart_data_read, uart_data_read_nxt : std_logic;
 
 begin
@@ -75,6 +77,7 @@ begin
                        tx_rdy_int <= '0';
                        new_tx_data <= '0';
                        uart_data_read <= '0';
+                       uart_int <= '0';
 
        elsif rising_edge(clk) then            
                        w1_st_co <= w1_st_co_nxt;
@@ -84,6 +87,7 @@ begin
                        new_tx_data <= new_tx_data_nxt;
                        tx_rdy_int <= tx_rdy;
                        uart_data_read <= uart_data_read_nxt;
+                       uart_int <= uart_int_nxt;
    end if;
 end process syn;
 
@@ -94,7 +98,7 @@ gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_r
 variable tmp_data  : gp_register_t;
 
 begin
-
+               uart_int_nxt <= '0';
                w1_st_co_nxt <= w1_st_co;
                w2_uart_config_nxt <= w2_uart_config;
                w3_uart_send_nxt <= w3_uart_send;
@@ -136,6 +140,7 @@ begin
        if new_bus_rx = '1' then
                w4_uart_receive_nxt(7 downto 0) <= rx_data;
                w1_st_co_nxt(17) <= '1';
+               uart_int_nxt <= '1';
        end if;
        
        if (uart_data_read = '1' and w1_st_co(17) = '1' and ext_reg.sel = '1') then