writeback_stage: differenzieren zwischen memory und extension geht ( btw wer sich...

[calu.git] / cpu / src / extension_uart_b.vhd

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 7dc28927b912a62294be61d7eac0eeac8d920a9f..5dd8774d76565c34f97fa37b6a957f79164e261e 100644 (file)
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -12,9 +12,9 @@ use work.extension_uart_pkg.all;
 architecture behav of extension_uart is
 
 signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send, w3_uart_send_nxt, w4_uart_receive, w4_uart_receive_nxt : gp_register_t;
-signal new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
+signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
 signal         bd_rate : baud_rate_l;
-
+signal rx_data : std_logic_vector(7 downto 0);
 begin
 
 
@@ -51,9 +51,8 @@ port map(
        bus_rx,
 
        --From/to sendlogic
-       w1_st_co(17),
-       w4_uart_receive(byte_t'range)
-       
+       new_bus_rx,
+       rx_data
 );
 
 
@@ -66,7 +65,8 @@ begin
                w2_uart_config <= (others=>'0');
                w3_uart_send <= (others=>'0');
                w4_uart_receive <= (others=>'0');
-
+               tx_rdy_int <= '0';
+               new_tx_data <= '0';
 
         elsif rising_edge(clk) then            
                w1_st_co <= w1_st_co_nxt;