added instruction rom/ram switch, added new data signaling bit in uart.

[calu.git] / cpu / src / extension_uart_b.vhd

diff --git a/cpu/src/extension_uart_b.vhd b/cpu/src/extension_uart_b.vhd
index 45150df71a87a78286eb50fdb4e716f9cc27a23f..2eda02bcd7b6a8390d20386d14c472b0d4c67a82 100644 (file)
--- a/cpu/src/extension_uart_b.vhd
+++ b/cpu/src/extension_uart_b.vhd
@@ -15,6 +15,9 @@ signal w1_st_co, w1_st_co_nxt, w2_uart_config, w2_uart_config_nxt, w3_uart_send,
 signal new_bus_rx,new_wb_data,  new_wb_data_nxt, new_tx_data, new_tx_data_nxt, tx_rdy, tx_rdy_int : std_logic;
 signal         bd_rate : baud_rate_l;
 signal rx_data : std_logic_vector(7 downto 0);
+
+signal uart_data_read, uart_data_read_nxt : std_logic;
+
 begin
 
 
@@ -62,29 +65,31 @@ port map(
 
 syn : process (clk, reset)
 begin
-        if (reset = RESET_VALUE) then
-               w1_st_co <= (others=>'0');
-               w2_uart_config(31 downto 16) <= (others=>'0');
-               -- todo mit einer konstante versehen
-               w2_uart_config(15 downto 0) <= x"01B2";
-               w3_uart_send <= (others=>'0');
-               w4_uart_receive <= (others=>'0');
-               tx_rdy_int <= '0';
-               new_tx_data <= '0';
-
-        elsif rising_edge(clk) then            
-               w1_st_co <= w1_st_co_nxt;
-               w2_uart_config <= w2_uart_config_nxt;
-               w3_uart_send <= w3_uart_send_nxt;
-               w4_uart_receive <= w4_uart_receive_nxt;
-               new_tx_data <= new_tx_data_nxt;
-               tx_rdy_int <= tx_rdy;
-        end if;
+   if (reset = RESET_VALUE) then
+                       w1_st_co <= (others=>'0');
+                       w2_uart_config(31 downto 16) <= (others=>'0');
+                       -- todo mit einer konstante versehen
+                       w2_uart_config(15 downto 0) <= x"01B2";
+                       w3_uart_send <= (others=>'0');
+                       w4_uart_receive <= (others=>'0');
+                       tx_rdy_int <= '0';
+                       new_tx_data <= '0';
+                       uart_data_read <= '0';
+
+       elsif rising_edge(clk) then            
+                       w1_st_co <= w1_st_co_nxt;
+                       w2_uart_config <= w2_uart_config_nxt;
+                       w3_uart_send <= w3_uart_send_nxt;
+                       w4_uart_receive <= w4_uart_receive_nxt;
+                       new_tx_data <= new_tx_data_nxt;
+                       tx_rdy_int <= tx_rdy;
+                       uart_data_read <= uart_data_read_nxt;
+   end if;
 end process syn;
 
 -------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
 
-gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx)
+gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read)
 
 variable tmp_data  : gp_register_t;
 
@@ -133,7 +138,10 @@ begin
                w1_st_co_nxt(17) <= '1';
        end if;
        
-
+       if (uart_data_read = '1' and w1_st_co(17) = '1' and ext_reg.sel = '1') then
+               w1_st_co_nxt(17) <= '0';
+       end if;
+       
 end process gwriten;
 
 gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive)
@@ -141,6 +149,9 @@ gread : process (clk,ext_reg,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receiv
 variable tmp_data  : gp_register_t;
 
 begin
+
+       uart_data_read_nxt <= '0';
+
        if ext_reg.sel = '1' and ext_reg.wr_en = '0' then
                case ext_reg.addr(1 downto 0) is
                when "00" => 
@@ -189,7 +200,8 @@ begin
                        end if;
                        data_out <= tmp_data;
                when "11" =>
-                       tmp_data := (others =>'0');                     
+                       tmp_data := (others =>'0');     
+                       uart_data_read_nxt <= '1';
                        if ext_reg.byte_en(0) = '1' then
                                tmp_data(byte_t'range) := w4_uart_receive(byte_t'range);
                        end if;