signal rx_data : std_logic_vector(7 downto 0);
signal uart_int_nxt : std_logic;
-
-signal uart_data_read, uart_data_read_nxt : std_logic;
+signal uart_data_read_nxt : std_logic;
begin
w4_uart_receive <= (others=>'0');
tx_rdy_int <= '0';
new_tx_data <= '0';
- uart_data_read <= '0';
uart_int <= '0';
elsif rising_edge(clk) then
w4_uart_receive <= w4_uart_receive_nxt;
new_tx_data <= new_tx_data_nxt;
tx_rdy_int <= tx_rdy;
- uart_data_read <= uart_data_read_nxt;
uart_int <= uart_int_nxt;
end if;
end process syn;
-------------------------- LESEN UND SCHREIBEN ANFANG ------------------------------------------------------------
-gwriten : process (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read)
+gwriten : process
+ (ext_reg,tx_rdy,w1_st_co,w2_uart_config,w3_uart_send,w4_uart_receive,tx_rdy_int, rx_data, new_bus_rx, uart_data_read_nxt)
variable tmp_data : gp_register_t;
uart_int_nxt <= '1';
end if;
- if (uart_data_read = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
+ if (uart_data_read_nxt = '1' and w1_st_co(1) = '1' and ext_reg.sel = '1') then
w1_st_co_nxt(1) <= '0';
end if;