begin
if (reset = RESET_VALUE) then
reg.status <= (others=>'0');
- reg.pointers <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,DATA_ADDR_WIDTH)));
+ reg.preg <= (others => (std_logic_vector(to_unsigned(DATA_END_ADDR,reg.preg(0)'length))));
elsif rising_edge(clk) then
reg <= reg_nxt;
end if;
end process syn;
-asyn : process (clk, reset, reg, psw_nxt, ext_reg, pval, pwr_en, pinc, paddr)
+asyn : process (clk, reset, reg, psw_nxt, ext_reg, pwr_en, pinc, paddr)
variable reg_nxt_v : gpm_internal;
variable incb : gp_register_t;
- variable sel_pval : gp_register_t;
+ variable sel_pval : std_logic_vector(reg.preg(0)'range);
variable data_out_v : gp_register_t;
variable data_v : gp_register_t;
case ext_reg.addr(1 downto 0) is
when "00" =>
if ext_reg.byte_en(0) = '1' then
- reg_nxt_v.psw := (data_v(0), data_v(1), data_v(3), data_v(2));
- psw <= reg_nxt_v.psw;
+ reg_nxt_v.status := (data_v(0), data_v(1), data_v(3), data_v(2));
+ psw <= reg_nxt_v.status;
end if;
when "01" =>
--STACK_POINTER
tmp_data := (others =>'0');
- tmp_data(tmp_data'high downto BYTE_ADDR) := reg.preg(0);
+ tmp_data(tmp_data'high downto BYTEADDR) := reg.preg(0);
if ext_reg.byte_en(0) = '1' then
tmp_data(byte_t'range) := data_v(byte_t'range);
end if;
if ext_reg.byte_en(1) = '1' then
- tmp_data((2*byte_t'length-1) downto byte_t'length) := data_v(2*byte_t'length-1) downto byte_t'length);
+ tmp_data((2*byte_t'length-1) downto byte_t'length) := data_v((2*byte_t'length-1) downto byte_t'length);
end if;
if ext_reg.byte_en(2) = '1' then
- tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := data_v(3*byte_t'length-1) downto 2*byte_t'length);
+ tmp_data((3*byte_t'length-1) downto 2*byte_t'length) := data_v((3*byte_t'length-1) downto 2*byte_t'length);
end if;
if ext_reg.byte_en(3) = '1' then
- tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := data_v(4*byte_t'length-1) downto 3*byte_t'length);
+ tmp_data((4*byte_t'length-1) downto 3*byte_t'length) := data_v((4*byte_t'length-1) downto 3*byte_t'length);
end if;
- reg_nxt_v.preg(0) := tmp_data(tmp_data'high downto BYTE_ADDR);
+ reg_nxt_v.preg(0) := tmp_data(tmp_data'high downto BYTEADDR);
when others => null;
end case;
end if;
- if (ext_reg.sel = '1') and wr_en = '0' then
+ if (ext_reg.sel = '1') and ext_reg.wr_en = '0' then
case ext_reg.addr(1 downto 0) is
when "00" =>
if ext_reg.byte_en(0) = '1' then
- data_out_v(3 downto 0) <= (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero);
+ data_out_v(3 downto 0) := (reg.status.sign, reg.status.carry, reg.status.oflo, reg.status.zero);
end if;
when "01" =>
--STACK_POINTER
- data_out_v(data_out_v'high downto BYTE_ADDR) := reg.preg(0);
+ data_out_v(data_out_v'high downto BYTEADDR) := reg.preg(0);
when others => null;
end case;
end if;
-
- sel_pval := reg_nxt_v.preg(unsigned(paddr));
+ sel_pval:= reg_nxt_v.preg(to_integer(unsigned(paddr)));
if pwr_en = '1' then
reg_nxt_v.preg(to_integer(unsigned(paddr))) := std_logic_vector(unsigned(sel_pval)+unsigned(incb));
data_out <= data_out_v;
pval <= (others =>'0');
- pval(pval'high downto BYTE_ADDR) <= sel_pval;
+ pval(pval'high downto BYTEADDR) <= sel_pval;
end process asyn;
end behav;