copyleft: gplv3 added and set repo to public

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index ccbfee3ed7cf7ad62fb31f172cb13d0371d2a406..17d6825d60f38ea702a7190a103857f0dbba0cbb 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -1,10 +1,31 @@
+--   `Deep Thought', a softcore CPU implemented on a FPGA
+--
+--  Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
+--  Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
+--  Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
+--  Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
+--  Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
+--
+--  This program is free software: you can redistribute it and/or modify
+--  it under the terms of the GNU General Public License as published by
+--  the Free Software Foundation, either version 3 of the License, or
+--  (at your option) any later version.
+--
+--  This program is distributed in the hope that it will be useful,
+--  but WITHOUT ANY WARRANTY; without even the implied warranty of
+--  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+--  GNU General Public License for more details.
+--
+--  You should have received a copy of the GNU General Public License
+--  along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
 library IEEE;
 use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
 use work.alu_pkg.all;
-use work.gpm_pkg.all;
+--use work.gpm_pkg.all;
 use work.extension_pkg.all;
 
 architecture behav of execute_stage is
@@ -19,7 +40,7 @@ signal psw : status_rec;
                signal ext_gpmp :  extmod_rec;
                signal data_out    : gp_register_t;
 
-signal pval : gp_register_t;
+signal pval, pval_nxt : gp_register_t;
 signal paddr : paddr_t;
 signal pinc, pwr_en : std_logic;
 
@@ -39,7 +60,7 @@ begin
 
 alu_inst : alu
 port map(clk, reset, condition, op_group, 
-         left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, alu_nxt,addr,data, pinc, pwr_en, paddr);
+         left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, pval_nxt, alu_nxt,addr,data, pinc, pwr_en, paddr);
 
 
 
@@ -55,7 +76,8 @@ port map(clk, reset, condition, op_group,
                        pinc,
                        pwr_en,
                        psw,
-                       pval
+                       pval,
+                       pval_nxt
                );
 
 
@@ -122,13 +144,20 @@ result_addr <= reg.res_addr;
 alu_jump <= reg.alu_jump;
 brpr <= reg.brpr;
 wr_en <= reg.wr_en;
+
 dmem <= alu_nxt.mem_op;
+
 --dmem <= reg.result(4);
+
 dmem_write_en <= alu_nxt.mem_en;
+
 --dmem_write_en <= reg.result(0);
 --dmem_write_en <= '1';
+
 hword <= alu_nxt.hw_op;
+
 --hword <= reg.result(1);
+
 byte_s <= alu_nxt.byte_op;
 
 --addr <= alu_nxt.result;