1 -- `Deep Thought', a softcore CPU implemented on a FPGA
3 -- Copyright (C) 2010 Markus Hofstaetter <markus.manrow@gmx.at>
4 -- Copyright (C) 2010 Martin Perner <e0725782@student.tuwien.ac.at>
5 -- Copyright (C) 2010 Stefan Rebernig <stefan.rebernig@gmail.com>
6 -- Copyright (C) 2010 Manfred Schwarz <e0725898@student.tuwien.ac.at>
7 -- Copyright (C) 2010 Bernhard Urban <lewurm@gmail.com>
9 -- This program is free software: you can redistribute it and/or modify
10 -- it under the terms of the GNU General Public License as published by
11 -- the Free Software Foundation, either version 3 of the License, or
12 -- (at your option) any later version.
14 -- This program is distributed in the hope that it will be useful,
15 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
16 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 -- GNU General Public License for more details.
19 -- You should have received a copy of the GNU General Public License
20 -- along with this program. If not, see <http://www.gnu.org/licenses/>.
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
26 use work.common_pkg.all;
28 --use work.gpm_pkg.all;
29 use work.extension_pkg.all;
31 architecture behav of execute_stage is
33 signal condition : condition_t;
34 signal op_group : op_info_t;
35 signal op_detail : op_opt_t;
36 signal left_operand, right_operand : gp_register_t;
37 signal alu_state, alu_nxt : alu_result_rec;
38 signal psw : status_rec;
40 signal ext_gpmp : extmod_rec;
41 signal data_out : gp_register_t;
43 signal pval, pval_nxt : gp_register_t;
44 signal paddr : paddr_t;
45 signal pinc, pwr_en : std_logic;
49 type exec_internal is record
50 result : gp_register_t;
57 signal reg, reg_nxt : exec_internal;
62 port map(clk, reset, condition, op_group,
63 left_operand, right_operand, dec_instr.displacement, dec_instr.prog_cnt, dec_instr.brpr, op_detail, alu_state, pval, pval_nxt, alu_nxt,addr,data, pinc, pwr_en, paddr);
67 gpmp_inst : extension_gpm
68 generic map (RESET_VALUE)
85 syn: process(clk, reset)
89 if reset = RESET_VALUE then
93 reg.result <= (others =>'0');
94 reg.res_addr <= (others => '0');
95 elsif rising_edge(clk) then
101 asyn: process(reset,dec_instr, alu_nxt, psw, reg,left_operand,right_operand)
104 condition <= dec_instr.condition;
105 op_group <= dec_instr.op_group;
106 op_detail <= dec_instr.op_detail;
110 alu_state <= (reg.result,dec_instr.daddr,psw,reg.alu_jump,reg.brpr,'0','0','0','0','0','0');
113 if reset = RESET_VALUE then
114 condition <= COND_NEVER;
119 reg_nxt.brpr <= alu_nxt.brpr;
120 reg_nxt.alu_jump <= alu_nxt.alu_jump;
121 reg_nxt.wr_en <= alu_nxt.reg_op;
122 reg_nxt.result <= alu_nxt.result;
123 reg_nxt.res_addr <= alu_nxt.result_addr;
127 forward: process(regfile_val, reg_we, reg_addr, dec_instr)
129 left_operand <= dec_instr.src1;
130 right_operand <= dec_instr.src2;
133 if dec_instr.saddr1 = reg_addr then
134 left_operand <= regfile_val;
136 if (dec_instr.saddr2 = reg_addr) and (dec_instr.op_detail(IMM_OPT) = '0') then
137 right_operand <= regfile_val;
142 result <= reg.result;
143 result_addr <= reg.res_addr;
144 alu_jump <= reg.alu_jump;
148 dmem <= alu_nxt.mem_op;
150 --dmem <= reg.result(4);
152 dmem_write_en <= alu_nxt.mem_en;
154 --dmem_write_en <= reg.result(0);
155 --dmem_write_en <= '1';
157 hword <= alu_nxt.hw_op;
159 --hword <= reg.result(1);
161 byte_s <= alu_nxt.byte_op;
163 --addr <= alu_nxt.result;
164 --data <= right_operand;
165 --byte_s <= reg.result(2);